| #
31a2dc69 |
| 15-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: pci: Assign pci irqs to all functions
We need walk through all functions within a PCI device and assign
their IRQs accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
x86: pci: Assign pci irqs to all functions
We need walk through all functions within a PCI device and assign
their IRQs accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
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| #
d81572c2 |
| 05-May-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-mpc85xx
|
| #
1131d4e2 |
| 05-May-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-marvell
|
| #
ff7e9cfc |
| 05-May-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mmc
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| #
3f2f1a00 |
| 05-May-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
|
| #
622da1c3 |
| 04-May-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
|
| #
283a08e5 |
| 27-Apr-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Check PIRQ routing table sanity in the F segment
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switc
x86: Check PIRQ routing table sanity in the F segment
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final table in the F segment as this one is
the one seen by the OS.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
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| #
b5b6b019 |
| 24-Apr-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chip
x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).
We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|