| 6525d51f | 08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases
Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases
Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.
Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| dd2cda3d | 08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2
powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 99d9c07e | 08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.
Signed-off-by: Kumar Gala <galak@kernel.crashing.or
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 9f43d799 | 08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move p1022ds slot code into board file
The code to map SERDES configs to slot names is board specific and not
chip specific. Thus it should live in board/freescale/p1022ds/ and not
in
powerpc/85xx: Move p1022ds slot code into board file
The code to map SERDES configs to slot names is board specific and not
chip specific. Thus it should live in board/freescale/p1022ds/ and not
in arch/powerpc/cpu/.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| c59e1b4d | 14-Jun-2010 |
Timur Tabi <timur@freescale.com> |
powerpc: add support for the Freescale P1022DS reference board
Specifics:
1) 36-bit only
2) Booting from NOR flash only
3) Environment stored in NOR flash only
4) No SPI support
5) No DIU support
powerpc: add support for the Freescale P1022DS reference board
Specifics:
1) 36-bit only
2) Booting from NOR flash only
3) Environment stored in NOR flash only
4) No SPI support
5) No DIU support
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 752bc335 | 28-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl: add LAW target to fsl_pci_info structure
Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that
we can capture the LAW target for a given PCI or PCIE controller. Also upd
fsl: add LAW target to fsl_pci_info structure
Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that
we can capture the LAW target for a given PCI or PCIE controller. Also update
the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the
LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure.
This will allow future PCI[E] code to configure the LAW target automatically,
rather than requiring each board to it for each PCI controller separately.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| ae391392 | 29-Mar-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for link stack & STAC on e5500
The e5500 has a link register stack and segment target address cache.
Its safe to enable these bits on older e500 cores as the bits are
imple
powerpc/85xx: Add support for link stack & STAC on e5500
The e5500 has a link register stack and segment target address cache.
Its safe to enable these bits on older e500 cores as the bits are
implemented in the register.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| f2d9a5da | 17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
powerpc 83xx/85xx: Merge lbc upmconfig code
Each platform had its own version of the upmconfig, despite the
init process being identical. Now that we have a spot for common
lbc code, create a commo
powerpc 83xx/85xx: Merge lbc upmconfig code
Each platform had its own version of the upmconfig, despite the
init process being identical. Now that we have a spot for common
lbc code, create a common upmconfig() there.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| e71755f8 | 17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
drivers/misc/fsl_law.c: Rearrange code to avoid duplication
The current code redefines functions based on FSL_CORENET_ vs not -
create macros/inlines instead that hide the differences.
Signed-off-b
drivers/misc/fsl_law.c: Rearrange code to avoid duplication
The current code redefines functions based on FSL_CORENET_ vs not -
create macros/inlines instead that hide the differences.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 70e02bca | 17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
mpc85xx: Add print_tlbcam() function
This dumps out the contents of TLB1 on 85xx-based systems.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crash
mpc85xx: Add print_tlbcam() function
This dumps out the contents of TLB1 on 85xx-based systems.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 4e63df30 | 17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
mpc85xx: tlb.c cleanups
Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code. Create a TSIZE_TO_BYTES ma
mpc85xx: tlb.c cleanups
Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code. Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| f51cdaf1 | 17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do th
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 8f3a7fa4 | 09-Jun-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtb
If we explicitly disabled a core remove it from the dtb we pass on to
the kernel.
Signed-off-by: Kumar Gala <galak@kernel.crashi
powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtb
If we explicitly disabled a core remove it from the dtb we pass on to
the kernel.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 22f292c7 | 01-Jun-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
| 929a2138 | 01-Jun-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Distinguish between incompatible SEC h/w types
CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomod
powerpc/8xxx: Distinguish between incompatible SEC h/w types
CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomodate incompatible code changes.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 7c619ddc | 28-Jun-2010 |
Ilya Yanok <yanok@emcraft.com> |
mpc8308: support for Freescale MPC8308 cpu
This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also sup
mpc8308: support for Freescale MPC8308 cpu
This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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| 2909ac03 | 25-May-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well
This patch adds some DDR(2) macros to all PPC4xx's equipped with
this IBM DDR1/2 controller.
Signed-off-by: Stefan Roese <sr@denx.d
ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well
This patch adds some DDR(2) macros to all PPC4xx's equipped with
this IBM DDR1/2 controller.
Signed-off-by: Stefan Roese <sr@denx.de>
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| 066003b2 | 25-May-2010 |
Stefan Roese <sr@denx.de> |
ppc4xx: Enable overwriting of default scan window for IBM DDR2 controller
This patch makes it possible to overwrite the default auto-calibration
scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] v
ppc4xx: Enable overwriting of default scan window for IBM DDR2 controller
This patch makes it possible to overwrite the default auto-calibration
scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] values) with
board specific values. The parameters of the weak default function are
corrected as well. This way we don't need the casts any more.
This feature will be used by an upcoming PPC460GT board port.
Signed-off-by: Stefan Roese <sr@denx.de>
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| 6e37a044 | 20-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition
Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of
struct ccsr_gur.
Signed-off-by: Timur Tabi <timur@free
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition
Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of
struct ccsr_gur.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 6ab4011b | 20-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
85xx: Add is_serdes_configured() support to MPC8536 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since the
85xx: Add is_serdes_configured() support to MPC8536 SERDES
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are
only ever connected on SERDES.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 3b439792 | 28-Apr-2010 |
Ron Madrid <ron_madrid@sbcglobal.net> |
mpc83xx: Add UPMA configuration to SIMPC8313
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by:
mpc83xx: Add UPMA configuration to SIMPC8313
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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| 8e98f5f7 | 27-Apr-2010 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx |
| 7e1afb62 | 20-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
dete
ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQ
The MPC83xx SERDES control is different from the other FSL PPC chips.
For now lets split it out so we can standardize on interfaces for
determining of a device on SERDES is configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
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| 3f0202ed | 21-Apr-2010 |
Lan Chunhe <b25806@freescale.com> |
mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar
mpc85xx: Add the ability to set LCRR[CLKDIV] to improve R/W speed of flash
Signed-off-by: Lan Chunhe <b25806@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 0c955daf | 14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022
clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <g
85xx: clean up the io_sel for PCI express of P1022
clean up the wrong io_sel for PCI express according to latest manual.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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