Revision tags: v9.1.0 |
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a71d9dfb |
| 30-Jun-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2
Argument ordering for setcond2 is:
output, a_low, a_high, b_low, b_high, cond
The test is supposed to be against b_low, not a_high.
Cc
tcg/optimize: Fix TCG_COND_TST* simplification of setcond2
Argument ordering for setcond2 is:
output, a_low, a_high, b_low, b_high, cond
The test is supposed to be against b_low, not a_high.
Cc: qemu-stable@nongnu.org Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240701024623.1265028-1-richard.henderson@linaro.org>
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8d65cda7 |
| 26-Mar-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Optimize setcond with zmask
If we can show that high bits of an input are zero, then we may optimize away some comparisons.
Signed-off-by: Richard Henderson <richard.henderson@linaro.
tcg/optimize: Optimize setcond with zmask
If we can show that high bits of an input are zero, then we may optimize away some comparisons.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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e25fe886 |
| 04-Apr-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Do not attempt to constant fold neg_vec
Split out the tail of fold_neg to fold_neg_no_const so that we can avoid attempting to constant fold vector negate.
Resolves: https://gitlab.co
tcg/optimize: Do not attempt to constant fold neg_vec
Split out the tail of fold_neg to fold_neg_no_const so that we can avoid attempting to constant fold vector negate.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2150 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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2911e9b9 |
| 26-Mar-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Fix sign_mask for logical right-shift
The 'sign' computation is attempting to locate the sign bit that has been repeated, so that we can test if that bit is known zero. That computati
tcg/optimize: Fix sign_mask for logical right-shift
The 'sign' computation is attempting to locate the sign bit that has been repeated, so that we can test if that bit is known zero. That computation can be zero if there are no known sign repetitions.
Cc: qemu-stable@nongnu.org Fixes: 93a967fbb57 ("tcg/optimize: Propagate sign info for shifting") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2248 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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ff202817 |
| 28-Feb-2024 |
Paolo Bonzini <pbonzini@redhat.com> |
tcg/optimize: fix uninitialized variable
The variables uext_opc and sext_opc are used without initialization if TCG_TARGET_extract_i{32,64}_valid returns false. The result, depending on the compile
tcg/optimize: fix uninitialized variable
The variables uext_opc and sext_opc are used without initialization if TCG_TARGET_extract_i{32,64}_valid returns false. The result, depending on the compiler, might be the generation of extract and sextract opcodes with invalid offset and count, or just random data in the TCG opcode stream.
Fixes: ceb9ee06b71 ("tcg/optimize: Handle TCG_COND_TST{EQ,NE}", 2024-02-03) Cc: Richard Henderson <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240228110641.287205-1-pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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fb04ab7d |
| 10-Jan-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported
After having performed other simplifications, lower any remaining test comparisons with AND.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linar
tcg/optimize: Lower TCG_COND_TST{EQ,NE} if unsupported
After having performed other simplifications, lower any remaining test comparisons with AND.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ceb9ee06 |
| 24-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Handle TCG_COND_TST{EQ,NE}
Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero
tcg/optimize: Handle TCG_COND_TST{EQ,NE}
Fold constant comparisons. Canonicalize "tst x,x" to equality vs zero. Canonicalize "tst x,sign" to sign test vs zero. Fold double-word comparisons with zero parts. Fold setcond of "tst x,pow2" to a bit extract.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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7e64b114 |
| 24-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2
Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper.
Reviewed-by: Philippe Math
tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2
Mirror the new do_constant_folding_cond1 by doing all argument and condition adjustment within one helper.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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246c4b72 |
| 24-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Split out do_constant_folding_cond1
Handle modifications to the arguments and condition in a single place.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richa
tcg/optimize: Split out do_constant_folding_cond1
Handle modifications to the arguments and condition in a single place.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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27cdb85d |
| 23-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Split out arg_is_const_val
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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f2457577 |
| 25-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Canonicalize sub2 with constants to add2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <2023102601
tcg/optimize: Canonicalize sub2 with constants to add2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-4-richard.henderson@linaro.org>
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6334a968 |
| 25-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Canonicalize subi to addi during optimization
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231
tcg/optimize: Canonicalize subi to addi during optimization
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20231026013945.1152174-3-richard.henderson@linaro.org>
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26aac97c |
| 23-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Split out arg_new_constant
Fixes a bug wherein raw uses of tcg_constant_internal do not have their TempOptInfo initialized.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Sig
tcg/optimize: Split out arg_new_constant
Fixes a bug wherein raw uses of tcg_constant_internal do not have their TempOptInfo initialized.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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3eaadaeb |
| 24-Aug-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Eliminate duplicate env store operations
Notice when a constant is stored to the same location twice.
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.hend
tcg: Eliminate duplicate env store operations
Notice when a constant is stored to the same location twice.
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ab84dc39 |
| 24-Aug-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Optimize env memory operations
Propagate stores to loads, loads to loads.
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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9f75e528 |
| 02-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Split out cmp_better_copy
Compare two temps for "better", split out from finding the best from a whole list. Use TCGKind, which already gives the proper priority.
Signed-off-by: Rich
tcg/optimize: Split out cmp_better_copy
Compare two temps for "better", split out from finding the best from a whole list. Use TCGKind, which already gives the proper priority.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0 |
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986cac1d |
| 09-Jan-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/optimize: Pipe OptContext into reset_ts
Will be needed in the next patch.
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Rich
tcg/optimize: Pipe OptContext into reset_ts
Will be needed in the next patch.
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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b701f195 |
| 25-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
The movcond opcode is now mandatory for backends to implement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1
tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}
The movcond opcode is now mandatory for backends to implement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231026041404.1229328-7-richard.henderson@linaro.org>
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d97f8f39 |
| 16-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Optimize past conditional branches
We already register allocate through extended basic blocks, optimize through extended basic blocks as well.
Signed-off-by: Richard Henderson <richard.henders
tcg: Optimize past conditional branches
We already register allocate through extended basic blocks, optimize through extended basic blocks as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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3635502d |
| 04-Aug-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Introduce negsetcond opcodes
Introduce a new opcode for negative setcond.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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8f7a840d |
| 13-Aug-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Fold deposit with zero to and
Inserting a zero into a value, or inserting a value into zero at offset 0 may be implemented with AND.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Rev
tcg: Fold deposit with zero to and
Inserting a zero into a value, or inserting a value into zero at offset 0 may be implemented with AND.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ad3d0e4d |
| 28-Mar-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h
Create tcg/tcg-op-common.h, moving everything that does not concern TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header instead of tcg-op
tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h
Create tcg/tcg-op-common.h, moving everything that does not concern TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header instead of tcg-op.h, in preparation for compiling tcg/ only once.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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fecccfcc |
| 16-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits, as we need one or two host registers to represent the guest address.
Create
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits, as we need one or two host registers to represent the guest address.
Create the new opcodes and update all users. Since we have not yet eliminated TARGET_LONG_BITS, only one of the two opcodes will ever be used, so we can get away with treating them the same in the backends.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0 |
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12fde9bc |
| 06-Nov-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add INDEX_op_qemu_{ld,st}_i128
Add opcodes for backend support for 128-bit memory operations.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@
tcg: Add INDEX_op_qemu_{ld,st}_i128
Add opcodes for backend support for 128-bit memory operations.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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732e89f4 |
| 05-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Replace tcg_abort with g_assert_not_reached
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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