e01e1c7e | 04-Oct-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/tricore: Use explicit little-endian LD/ST API
The TriCore architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc i
target/tricore: Use explicit little-endian LD/ST API
The TriCore architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/tricore/); \ done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-15-philmd@linaro.org>
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2a99b2af | 04-Oct-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/loongarch: Use explicit little-endian LD/ST API
The LoongArch architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for a
target/loongarch: Use explicit little-endian LD/ST API
The LoongArch architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/loongarch/); \ done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-13-philmd@linaro.org>
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186f19cf | 04-Oct-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/avr: Use explicit little-endian LD/ST API
The AVR architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc in uw w l
target/avr: Use explicit little-endian LD/ST API
The AVR architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/avr/); \ done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-11-philmd@linaro.org>
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ae412c02 | 04-Oct-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/hexagon: Use explicit little-endian LD/ST API
The Hexagon architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc i
target/hexagon: Use explicit little-endian LD/ST API
The Hexagon architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/hexagon/); \ done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-8-philmd@linaro.org>
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c9ddc704 | 04-Oct-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/alpha: Use explicit little-endian LD/ST API
The Alpha architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc in uw
target/alpha: Use explicit little-endian LD/ST API
The Alpha architecture uses little endianness. Directly use the little-endian LD/ST API.
Mechanical change using:
$ end=le; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(/st${acc}_${end}_p(/" \ $(git grep -wlE '(ld|st)t?u?[wlq]_p' target/alpha/); \ done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-7-philmd@linaro.org>
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e63b5f64 | 04-Oct-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/alpha: Replace ldtul_p() -> ldq_p()
The Alpha target is only built for 64-bit. Using ldtul_p() is pointless, replace by ldq_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldq_p/' $(
target/alpha: Replace ldtul_p() -> ldq_p()
The Alpha target is only built for 64-bit. Using ldtul_p() is pointless, replace by ldq_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldq_p/' $(git grep -wl ldtul_p target/alpha/)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-4-philmd@linaro.org>
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39914ae8 | 04-Oct-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/hexagon: Replace ldtul_p() -> ldl_p()
The Hexagon target is only built for 32-bit. Using ldtul_p() is pointless, replace by ldl_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldl_p/
target/hexagon: Replace ldtul_p() -> ldl_p()
The Hexagon target is only built for 32-bit. Using ldtul_p() is pointless, replace by ldl_p().
Mechanical change doing:
$ sed -i -e 's/ldtul_p/ldl_p/' \ $(git grep -wl ldtul_p target/hexagon/)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004163042.85922-3-philmd@linaro.org>
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e530581e | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Fix alignment fault priority in get_phys_addr_lpae
Now that we have the MemOp for the access, we can order the alignment fault caused by memory type before the permission fault for the p
target/arm: Fix alignment fault priority in get_phys_addr_lpae
Now that we have the MemOp for the access, we can order the alignment fault caused by memory type before the permission fault for the page.
For subsequent page hits, permission and stage 2 checks are known to pass, and so the TLB_CHECK_ALIGNED fault raised in generic code is not mis-ordered.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1ba3cb88 | 07-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Implement TCGCPUOps.tlb_fill_align
Fill in the tlb_fill_align hook. Handle alignment not due to memory type, since that's no longer handled by generic code. Pass memop to get_phys_addr.
target/arm: Implement TCGCPUOps.tlb_fill_align
Fill in the tlb_fill_align hook. Handle alignment not due to memory type, since that's no longer handled by generic code. Pass memop to get_phys_addr.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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64bda510 | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Move device detection earlier in get_phys_addr_lpae
Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if bloc
target/arm: Move device detection earlier in get_phys_addr_lpae
Determine cache attributes, and thence Device vs Normal memory, earlier in the function. We have an existing regime_is_stage2 if block into which this can be slotted.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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c053f40b | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Pass MemOp to get_phys_addr_lpae
Pass the value through from get_phys_addr_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Revie
target/arm: Pass MemOp to get_phys_addr_lpae
Pass the value through from get_phys_addr_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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21e5a287 | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Pass MemOp through get_phys_addr_twostage
Pass memop through get_phys_addr_twostage with its recursion with get_phys_addr_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: P
target/arm: Pass MemOp through get_phys_addr_twostage
Pass memop through get_phys_addr_twostage with its recursion with get_phys_addr_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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c6cd9f9f | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Pass MemOp to get_phys_addr_nogpc
Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr_gpc and get_phys_addr_with_space_nogpc.
Reviewed-by: He
target/arm: Pass MemOp to get_phys_addr_nogpc
Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr_gpc and get_phys_addr_with_space_nogpc.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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5458670b | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Pass MemOp to get_phys_addr_gpc
Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: P
target/arm: Pass MemOp to get_phys_addr_gpc
Zero is the safe do-nothing value for callers to use. Pass the value through from get_phys_addr.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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29b4d7db | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Pass MemOp to get_phys_addr_with_space_nogpc
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@
target/arm: Pass MemOp to get_phys_addr_with_space_nogpc
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ec2c9337 | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Pass MemOp to get_phys_addr
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signe
target/arm: Pass MemOp to get_phys_addr
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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99746de6 | 07-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement TCGCPUOps.tlb_fill_align
Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we can recognize alignment exceptions in the correct priority order.
Resolves: https://b
target/hppa: Implement TCGCPUOps.tlb_fill_align
Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we can recognize alignment exceptions in the correct priority order.
Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=219339 Tested-by: Helge Deller <deller@gmx.de> Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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5d29587b | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Handle alignment faults in hppa_get_physical_address
In Chapter 5, Interruptions, the group 3 exceptions lists "Unaligned data reference trap" has higher priority than "Data memory brea
target/hppa: Handle alignment faults in hppa_get_physical_address
In Chapter 5, Interruptions, the group 3 exceptions lists "Unaligned data reference trap" has higher priority than "Data memory break trap".
Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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d73d4a5d | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Fix priority of T, D, and B page faults
Drop the 'else' so that ret is overridden with the highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X") Reviewed-by: Helg
target/hppa: Fix priority of T, D, and B page faults
Drop the 'else' so that ret is overridden with the highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X") Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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32142b80 | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Perform access rights before protection id check
In Chapter 5, Interruptions, the group 3 exceptions lists "Data memory access rights trap" in priority order ahead of "Data memory prote
target/hppa: Perform access rights before protection id check
In Chapter 5, Interruptions, the group 3 exceptions lists "Data memory access rights trap" in priority order ahead of "Data memory protection ID trap".
Swap these checks in hppa_get_physical_address.
Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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4e6939c9 | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Add MemOp argument to hppa_get_physical_address
Just add the argument, unused at this point. Zero is the safe do-nothing value for all callers.
Reviewed-by: Helge Deller <deller@gmx.de
target/hppa: Add MemOp argument to hppa_get_physical_address
Just add the argument, unused at this point. Zero is the safe do-nothing value for all callers.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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c5809eee | 04-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
include/exec/memop: Rename get_alignment_bits
Rename to use "memop_" prefix, like other functions that operate on MemOp.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daud
include/exec/memop: Rename get_alignment_bits
Rename to use "memop_" prefix, like other functions that operate on MemOp.
Reviewed-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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ac2fb86a | 12-Sep-2024 |
Ilya Leoshkevich <iii@linux.ibm.com> |
target/i386/gdbstub: Expose orig_ax
Copy XML files describing orig_ax from GDB and glue them with CPUX86State.orig_ax.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: I
target/i386/gdbstub: Expose orig_ax
Copy XML files describing orig_ax from GDB and glue them with CPUX86State.orig_ax.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240912093012.402366-5-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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e7a4427a | 12-Sep-2024 |
Ilya Leoshkevich <iii@linux.ibm.com> |
target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg()
i386 gdbstub handles both i386 and x86_64. Factor out two functions for reading and writing registers without knowing their bitness.
target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg()
i386 gdbstub handles both i386 and x86_64. Factor out two functions for reading and writing registers without knowing their bitness.
While at it, simplify the TARGET_LONG_BITS == 32 case.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240912093012.402366-4-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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fe678c45 | 10-Oct-2024 |
Paolo Bonzini <pbonzini@redhat.com> |
tcg: remove singlestep_enabled from DisasContextBase
It is used in a couple of places only, both within the same target. Those can use the cflags just as well, so remove the separate field.
Signed-
tcg: remove singlestep_enabled from DisasContextBase
It is used in a couple of places only, both within the same target. Those can use the cflags just as well, so remove the separate field.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20241010083641.1785069-1-pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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