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b74588a4 |
| 04-Jun-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180604' into staging migration/next for 20180604 # gpg: Signature made Mon 04 Jun 2018 05:14:24 BST # gpg:
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180604' into staging migration/next for 20180604 # gpg: Signature made Mon 04 Jun 2018 05:14:24 BST # gpg: using RSA key F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" # gpg: aka "Juan Quintela <quintela@trasno.org>" # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * remotes/juanquintela/tags/migration/20180604: migration: not wait RDMA_CM_EVENT_DISCONNECTED event after rdma_disconnect migration: remove unnecessary variables len in QIOChannelRDMA migration: Don't activate block devices if using -S migration: discard non-migratable RAMBlocks migration: introduce decompress-error-check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
16367054 |
| 04-Jun-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into staging tcg-next queue # gpg: Signature made Sat 02 Jun 2018 00:12:42 BST # gpg: using
Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into staging tcg-next queue # gpg: Signature made Sat 02 Jun 2018 00:12:42 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/tcg-next-pull-request: tcg: Pass tb and index to tcg_gen_exit_tb separately Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
07ea28b4 |
| 30-May-2018 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Pass tb and index to tcg_gen_exit_tb separately Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more s
tcg: Pass tb and index to tcg_gen_exit_tb separately Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
a9cb55a3 |
| 14-May-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging Block pull request * Support -drive cache.direct=off live migration for POSIX files #
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging Block pull request * Support -drive cache.direct=off live migration for POSIX files # gpg: Signature made Sat 12 May 2018 10:27:51 BST # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: block/file-posix: add x-check-page-cache=on|off option block/file-posix: implement bdrv_co_invalidate_cache() on Linux checkpatch: reduce MAINTAINERS update message frequency checkpatch: emit a warning on file add/move/delete checkpatch: ignore email headers better checkpatch: check utf-8 content from a commit log when it's missing from charset checkpatch: add a --strict check for utf-8 in commit logs blockjob: drop block_job_pause/resume_all() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
bbd87423 |
| 14-May-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging tracing patches Just a MAINTAINERS file update for tracing files. # gpg: Signature ma
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging tracing patches Just a MAINTAINERS file update for tracing files. # gpg: Signature made Fri 11 May 2018 19:28:34 BST # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: MAINTAINERS: Add trace-events and qemu-option-trace.texi to tracing section Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
9ba1733a |
| 14-May-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * Don't silently truncate extremely long words in the command line * dtc configure fixes * MemoryRegionC
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * Don't silently truncate extremely long words in the command line * dtc configure fixes * MemoryRegionCache second try * Deprecated option removal * add support for Hyper-V reenlightenment MSRs # gpg: Signature made Fri 11 May 2018 13:33:46 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (29 commits) rename included C files to foo.inc.c, remove osdep.h pc-dimm: fix error messages if no slots were defined build: Silence dtc directory creation shippable: Remove Debian 8 libfdt kludge configure: Display if libfdt is from system or git configure: Really use local libfdt if the system one is too old i386/kvm: add support for Hyper-V reenlightenment MSRs qemu-doc: provide details of supported build platforms qemu-options: Remove deprecated -no-kvm-irqchip qemu-options: Remove deprecated -no-kvm-pit-reinjection qemu-options: Bail out on unsupported options instead of silently ignoring them qemu-options: Remove remainders of the -tdf option qemu-options: Mark -virtioconsole as deprecated target/i386: sev: fix memory leaks opts: don't silently truncate long option values opts: don't silently truncate long parameter keys accel: use g_strsplit for parsing accelerator names update-linux-headers: drop hyperv.h qemu-thread: always keep the posix wrapper layer exec: reintroduce MemoryRegion caching ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
f5583c52 |
| 11-May-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-excepti
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510' into staging target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for multiply-add corner case * arm: isolate and clean up DTB generation * implement Arm v8.1-Atomics extension * Fix some bugs and missing instructions in the v8.2-FP16 extension # gpg: Signature made Thu 10 May 2018 18:44:34 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits) target/arm: Clear SVE high bits for FMOV target/arm: Fix float16 to/from int16 target/arm: Implement vector shifted FCVT for fp16 target/arm: Implement vector shifted SCVF/UCVF for fp16 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only target/arm: Implement CAS and CASP target/arm: Fill in disas_ldst_atomic target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/riscv: Use new atomic min/max expanders tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add tcg: Introduce atomic helpers for integer min/max target/xtensa: Use new min/max expanders target/arm: Use new min/max expanders tcg: Introduce helpers for integer min/max atomic.h: Work around gcc spurious "unused value" warning make sure that we aren't overwriting mc->get_hotplug_handler by accident arm/boot: split load_dtb() from arm_load_kernel() platform-bus-device: use device plug callback instead of machine_done notifier pc: simplify MachineClass::get_hotplug_handler handling softfloat: Handle default NaN mode after pickNaNMulAdd, not before ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/riscv/translate.c
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#
c74e62ee |
| 11-May-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth/tags/cota-target-pull-request' into staging * Fix all next_page checks for overflow. * Convert six targets to the translator loop. # gp
Merge remote-tracking branch 'remotes/rth/tags/cota-target-pull-request' into staging * Fix all next_page checks for overflow. * Convert six targets to the translator loop. # gpg: Signature made Wed 09 May 2018 18:20:43 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/cota-target-pull-request: (28 commits) target/riscv: convert to TranslatorOps target/riscv: convert to DisasContextBase target/riscv: convert to DisasJumpType target/openrisc: convert to TranslatorOps target/openrisc: convert to DisasContextBase target/s390x: convert to TranslatorOps target/s390x: convert to DisasContextBase target/s390x: convert to DisasJumpType target/mips: convert to TranslatorOps target/mips: use *ctx for DisasContext target/mips: convert to DisasContextBase target/mips: convert to DisasJumpType target/mips: use lookup_and_goto_ptr on BS_STOP target/sparc: convert to TranslatorOps target/sparc: convert to DisasContextBase target/sparc: convert to DisasJumpType target/sh4: convert to TranslatorOps translator: merge max_insns into DisasContextBase target/mips: avoid integer overflow in next_page PC check target/s390x: avoid integer overflow in next_page PC check ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: ppc-for-2.13-20180504, ppc-for-2.13-20180427, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, ppc-for-2.12-20180410, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, ppc-for-2.12-20180319, ppc-for-2.12-20180315, ppc-for-2.12-20180306, ppc-for-2.12-20180302, ppc-for-2.12-20180216 |
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#
6e61bc94 |
| 15-Feb-2018 |
Emilio G. Cota <cota@braap.org> |
target/sparc: convert to TranslatorOps Notes: - Moved the cross-page check from the end of translate_insn to init_disas_context. Reviewed-by: Richard Henderson <richa
target/sparc: convert to TranslatorOps Notes: - Moved the cross-page check from the end of translate_insn to init_disas_context. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
af00be49 |
| 14-Feb-2018 |
Emilio G. Cota <cota@braap.org> |
target/sparc: convert to DisasContextBase Notes: - pc and npc are left unmodified, since they can point to out-of-TB jump targets. - Got rid of last_pc in gen_interme
target/sparc: convert to DisasContextBase Notes: - pc and npc are left unmodified, since they can point to out-of-TB jump targets. - Got rid of last_pc in gen_intermediate_code(), using base.pc_next instead. Only update pc_next (1) on a breakpoint (so that tb->size includes the insn), and (2) after reading the current instruction from memory. This allows us to use base.pc_next in the BP check, which is what the translator loop does. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
c5e6ccdf |
| 14-Feb-2018 |
Emilio G. Cota <cota@braap.org> |
target/sparc: convert to DisasJumpType Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Artyom Tarasenko <atar4q
target/sparc: convert to DisasJumpType Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
20f59d12 |
| 09-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Fri 09 Mar 2018 14:54:33 GMT # gpg: using RSA key F30C38BD
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Fri 09 Mar 2018 14:54:33 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: target/m68k: implement ftentox target/m68k: implement ftwotox target/m68k: implement fetox target/m68k: implement flog2 target/m68k: implement flog10 target/m68k: implement flogn target/m68k: implement flognp1 target/m68k: define floatx80_move() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
e4ae62b8 |
| 09-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging # gpg: Signature made Fri 09 Mar 2018 13:19:02 GMT # gpg: using RSA key 9CA4ABB381AB73
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging # gpg: Signature made Fri 09 Mar 2018 13:19:02 GMT # gpg: using RSA key 9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: vl: introduce vm_shutdown() virtio-scsi: fix race between .ioeventfd_stop() and vq handler virtio-blk: fix race between .ioeventfd_stop() and vq handler block: add aio_wait_bh_oneshot() virtio-blk: dataplane: Don't batch notifications if EVENT_IDX is present README: Fix typo 'git-publish' block: Fix qemu crash when using scsi-block Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d9bbfea6 |
| 09-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-upstream-v8.2' into staging QEMU RISC-V Emulation Support (RV64GC, RV32GC) This release renames the SiFive machines to si
Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-upstream-v8.2' into staging QEMU RISC-V Emulation Support (RV64GC, RV32GC) This release renames the SiFive machines to sifive_e and sifive_u to represent the SiFive Everywhere and SiFive Unleashed platforms. SiFive has configurable soft-core IP, so it is intended that these machines will be extended to enable a variety of SiFive IP blocks. The CPU definition infrastructure has been improved and there are now vendor CPU modules including the SiFiVe E31, E51, U34 and U54 cores. The emulation accuracy for the E series has been improved by disabling the MMU for the E series. S mode has been disabled on cores that only support M mode and U mode. The two Spike machines that support two privileged ISA versions have been coalesced into one file. This series has Signed-off-by from the core contributors. *** Known Issues *** * Disassembler has some checkpatch warnings for the sake of code brevity * scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length * PMP (Physical Memory Protection) is as-of-yet unused and needs testing *** Changelog *** v8.2 * Rebase v8.1 * Fix missed case of renaming spike_v1.9 to spike_v1.9.1 v8 * Added linux-user/riscv/target_elf.h during rebase * Make resetvec configurable and clear mpp and mie on reset * Use SiFive E31, E51, U34 and U54 cores in SiFive machines * Define SiFive E31, E51, U34 and U54 cores * Refactor CPU core definition in preparation for vendor cores * Prevent S or U mode unless S or U extensions are present * SiFive E Series cores have no MMU * SiFive E Series cores have U mode * Make privileged ISA v1.10 implicit in CPU types * Remove DRAM_BASE and EXT_IO_BASE as they vary by machine * Correctly handle mtvec and stvec alignment with respect to RVC * Print more machine mode state in riscv_cpu_dump_state * Make riscv_isa_string use compact extension order method * Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change * Parameterize spike v1.9.1 config string * Coalesce spike_v1.9.1 and spike_v1.10 machines * Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u v7 * Make spike_v1.10 the default machine * Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version * Remove empty target/riscv/trace-events file * Monitor ROM 32-bit reset code needs to be target endian * Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h * Add -initrd support to the virt board * Fix naming in spike machine interface header * Update copyright notice on RISC-V Spike machines * Update copyright notice on RISC-V HTIF Console device * Change CPU Core and translator to GPLv2+ * Change RISC-V Disassembler to GPLv2+ * Change SiFive Test Finisher to GPLv2+ * Change SiFive CLINT to GPLv2+ * Change SiFive PRCI to GPLv2+ * Change SiFive PLIC to GPLv2+ * Change RISC-V spike machines to GPLv2+ * Change RISC-V virt machine to GPLv2+ * Change SiFive E300 machine to GPLv2+ * Change SiFive U500 machine to GPLv2+ * Change RISC-V Hart Array to GPLv2+ * Change RISC-V HTIF device to GPLv2+ * Change SiFiveUART device to GPLv2+ v6 * Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax * Remove some unnecessary commented debug statements * Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix * Define all CPU variants for linux-user * qemu_log calls require trailing \n * Replace PLIC printfs with qemu_log * Tear out unused HTIF code and eliminate shouting debug messages * Fix illegal instruction when sfence.vma is passed (rs2) arguments * Make updates to PTE accessed and dirty bits atomic * Only require atomic PTE updates on MTTCG enabled guests * Page fault if accessed or dirty bits can't be updated * Fix get_physical_address PTE reads and writes on riscv32 * Remove erroneous comments from the PLIC * Default enable MTTCG * Make WFI less conservative * Unify local interrupt handling * Expunge HTIF interrupts * Always access mstatus.mip under a lock * Don't implement rdtime/rdtimeh in system mode (bbl emulates them) * Implement insreth/cycleh for rv32 and always enable user-mode counters * Add GDB stub support for reading and writing CSRs * Rename ENABLE_CHARDEV #ifdef from HTIF code * Replace bad HTIF ELF code with load_elf symbol callback * Convert chained if else fault handlers to switch statements * Use RISCV exception codes for linux-user page faults v5 * Implement NaN-boxing for flw, set high order bits to 1 * Use float_muladd_negate_* flags to floatXX_muladd * Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax * Fix TARGET_NR_syscalls * Update linux-user/riscv/syscall_nr.h * Fix FENCE.I, needs to terminate translation block * Adjust unusual convention for interruptno >= 0 v4 * Add @riscv: since 2.12 to CpuInfoArch * Remove misleading little-endian comment from load_kernel * Rename cpu-model property to cpu-type * Drop some unnecessary inline function attributes * Don't allow GDB to set value of x0 register * Remove unnecessary empty property lists * Add Test Finisher device to implement poweroff in virt machine * Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior * Store fflags data in fp_status * Purge runtime users of helper_raise_exception * Fix validate_csr * Tidy gen_jalr * Tidy immediate shifts * Add gen_exception_inst_addr_mis * Add gen_exception_debug * Add gen_exception_illegal * Tidy helper_fclass_* * Split rounding mode setting to a new function * Enforce MSTATUS_FS via TB flags * Implement acquire/release barrier semantics * Use atomic operations as required * Fix FENCE and FENCE_I * Remove commented code from spike machines * PAGE_WRITE permissions can be set on loads if page is already dirty * The result of format conversion on an NaN must be a quiet NaN * Add missing process_queued_cpu_work to riscv linux-user * Remove float(32|64)_classify from cpu.h * Removed nonsensical unions aliasing the same type * Use uintN_t instead of uintN_fast_t in fpu_helper.c * Use macros for FPU exception values in softfloat_flags_to_riscv * Move code to set round mode into set_fp_round_mode function * Convert set_fp_exceptions from a macro to an inline function * Convert round mode helper into an inline function * Make fpu_helper ieee_rm array static const * Include cpu_mmu_index in cpu_get_tb_cpu_state flags * Eliminate MPRV influence on mmu_index * Remove unrecoverable do_unassigned_access function * Only update PTE accessed and dirty bits if necessary * Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx * Remove buggy support for misa writes. misa writes are optional and are not implemented in any known hardware * Always set PTE read or execute permissions during page walk * Reorder helper function declarations to match order in helper.c * Remove redundant variable declaration in get_physical_address * Remove duplicated code from get_physical_address * Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug v3 * Fix indentation in PMP and HTIF debug macros * Fix disassembler checkpatch open brace '{' on next line errors * Fix trailing statements on next line in decode_inst_decompress * NOTE: the other checkpatch issues have been reviewed previously v2 * Remove redundant NULL terminators from disassembler register arrays * Change disassembler register name arrays to const * Refine disassembler internal function names * Update dates in disassembler copyright message * Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work * Use ULL suffix on 64-bit constants * Move riscv_cpu_mmu_index from cpu.h to helper.c * Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c * Remove redundant TARGET_HAS_ICE from cpu.h * Use qemu_irq instead of void* for irq definition in cpu.h * Remove duplicate typedef from struct CPURISCVState * Remove redundant g_strdup from cpu_register * Remove redundant tlb_flush from riscv_cpu_reset * Remove redundant mode calculation from get_physical_address * Remove redundant debug mode printf and dcsr comment * Remove redundant clearing of MSB for bare physical addresses * Use g_assert_not_reached for invalid mode in get_physical_address * Use g_assert_not_reached for unreachable checks in get_physical_address * Use g_assert_not_reached for unreachable type in raise_mmu_exception * Return exception instead of aborting for misaligned fetches * Move exception defines from cpu.h to cpu_bits.h * Remove redundant breakpoint control definitions from cpu_bits.h * Implement riscv_cpu_unassigned_access exception handling * Log and raise exceptions for unimplemented CSRs * Match Spike HTIF exit behavior - don’t print TEST-PASSED * Make frm,fflags,fcsr writes trap when mstatus.FS is clear * Use g_assert_not_reached for unreachable invalid mode * Make hret,uret,dret generate illegal instructions * Move riscv_cpu_dump_state and int/fpr regnames to cpu.c * Lift interrupt flag and mask into constants in cpu_bits.h * Change trap debugging to use qemu_log_mask LOG_TRACE * Change CSR debugging to use qemu_log_mask LOG_TRACE * Change PMP debugging to use qemu_log_mask LOG_TRACE * Remove commented code from pmp.c * Change CpuInfoRISCV qapi schema docs to Since 2.12 * Change RV feature macro to use target_ulong cast * Remove riscv_feature and instead use misa extension flags * Make riscv_flush_icache_syscall a no-op * Undo checkpatch whitespace fixes in unrelated linux-user code * Remove redudant constants and tidy up cpu_bits.h * Make helper_fence_i a no-op * Move include "exec/cpu-all" to end of cpu.h * Rename set_privilege to riscv_set_mode * Move redundant forward declaration for cpu_riscv_translate_address * Remove TCGV_UNUSED from riscv_translate_init * Add comment to pmp.c stating the code is untested and currently unused * Use ctz to simplify decoding of PMP NAPOT address ranges * Change pmp_is_in_range to use than equal for end addresses * Fix off by one error in pmp_update_rule * Rearrange PMP_DEBUG so that formatting is compile-time checked * Rearrange trap debugging so that formatting is compile-time checked * Rearrange PLIC debugging so that formatting is compile-time checked * Use qemu_log/qemu_log_mask for HTIF logging and debugging * Move exception and interrupt names into cpu.c * Add Palmer Dabbelt as a RISC-V Maintainer * Rebase against current qemu master branch v1 * initial version based on forward port from riscv-qemu repository *** Background *** "RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation." The QEMU RISC-V port has been developed and maintained out-of-tree for several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V Privileged specification has evolved substantially over this period but has recently been solidifying. The RISC-V Base ISA has been frozon for some time and the Privileged ISA, GCC toolchain and Linux ABI are now quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU Maintainer and hope to support upstreaming the port. There are multiple vendors taping out, preparing to ship, or shipping silicon that implements the RISC-V Privileged ISA Version 1.10. There are also several RISC-V Soft-IP cores implementing Privileged ISA Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform and the U54‑MC RISC-V Core IP, among many more implementations from a variety of vendors. See https://riscv.org/ for more details. RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first half of 2016. RISC-V support is now available in LLVM top-of-tree and the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year and is available in the Linux 4.15 release. GLIBC 2.27 added support for the RISC-V ISA running on Linux (requires at least binutils-2.30, gcc-7.3.0, and linux-4.15). We believe it is timely to submit the RISC-V QEMU port for upstream review with the goal of incorporating RISC-V support into the upcoming QEMU 2.12 release. The RISC-V QEMU port is still under active development, mostly with respect to device emulation, the addition of Hypervisor support as specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector support once the first draft is finalized later this year. We believe now is the appropriate time for RISC-V QEMU development to be carried out in the main QEMU repository as the code will benefit from more rigorous review. The RISC-V QEMU port currently supports all the ISA extensions that have been finalized and frozen in the Base ISA. Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki Instructions for building a busybox+dropbear root image, BBL (Berkeley Boot Loader) and linux kernel image for use with the RISC-V QEMU 'virt' machine: https://github.com/michaeljclark/busybear-linux *** Overview *** The RISC-V QEMU port implements the following specifications: * RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1 * RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10 The RISC-V QEMU port supports the following instruction set extensions: * RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU) * RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU) The RISC-V QEMU port adds the following targets to QEMU: * riscv32-softmmu * riscv64-softmmu * riscv32-linux-user * riscv64-linux-user The RISC-V QEMU port supports the following hardware: * HTIF Console (Host Target Interface) * SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs * SiFive PLIC (Platform Level Interrupt Controller) * SiFive Test (Test Finisher) for exiting simulation * SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented * VirtIO MMIO (GPEX PCI support will be added in a future patch) * Generic 16550A UART emulation using 'hw/char/serial.c' * MTTCG and SMP support (PLIC and CLINT) on the 'virt' machine The RISC-V QEMU full system emulator supports 5 machines: * 'spike_v1.9.1', CLINT, PLIC, HTIF console, config-string, Priv v1.9.1 * 'spike_v1.10', CLINT, PLIC, HTIF console, device-tree, Priv v1.10 * 'sifive_e', CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10 * 'sifive_u', CLINT, PLIC, SiFive UART, device-tree, Priv v1.10 * 'virt', CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10 This is a list of RISC-V QEMU Port Contributors: * Alex Suykov * Andreas Schwab * Antony Pavlov * Bastian Koppelmann * Bruce Hoult * Chih-Min Chao * Daire McNamara * Darius Rad * David Abdurachmanov * Hesham Almatary * Ivan Griffin * Jim Wilson * Kito Cheng * Michael Clark * Palmer Dabbelt * Richard Henderson * Sagar Karandikar * Shea Levy * Stefan O'Rear Notes: * contributor email addresses available off-list on request. * checkpatch has been run on all 23 patches. * checkpatch exceptions are noted in patches that have errors. * passes "make check" on full build for all targets * tested riscv-linux-4.6.2 on 'spike_v1.9.1' machine * tested riscv-linux-4.15 on 'spike_v1.10' and 'virt' machines * tested SiFive HiFive1 binaries in 'sifive_e' machine * tested RV64 on 32-bit i386 This patch series includes the following patches: # gpg: Signature made Thu 08 Mar 2018 19:40:20 GMT # gpg: using DSA key 6BF1D7B357EF3E4F # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>" # gpg: aka "Michael Clark <mjc@sifive.com>" # gpg: aka "Michael Clark <michael@metaparadigm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7C99 930E B17C D8BA 073D 5EFA 6BF1 D7B3 57EF 3E4F * remotes/riscv/tags/riscv-qemu-upstream-v8.2: (23 commits) RISC-V Build Infrastructure SiFive Freedom U Series RISC-V Machine SiFive Freedom E Series RISC-V Machine SiFive RISC-V PRCI Block SiFive RISC-V UART Device RISC-V VirtIO Machine SiFive RISC-V Test Finisher RISC-V Spike Machines SiFive RISC-V PLIC Block SiFive RISC-V CLINT Block RISC-V HART Array RISC-V HTIF Console Add symbol table callback interface to load_elf RISC-V Linux User Emulation RISC-V Physical Memory Protection RISC-V TCG Code Generation RISC-V GDB Stub RISC-V FPU Support RISC-V CPU Helpers RISC-V Disassembler ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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f6d81cde |
| 08-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-shippable-disable-ppc-080318-1' into staging One fix to disable broken ppc cross-compile test on shippable # gpg: Signature m
Merge remote-tracking branch 'remotes/stsquad/tags/pull-shippable-disable-ppc-080318-1' into staging One fix to disable broken ppc cross-compile test on shippable # gpg: Signature made Thu 08 Mar 2018 15:00:23 GMT # gpg: using RSA key FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-shippable-disable-ppc-080318-1: .shippable.yml: disable powerpc-cross image Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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83d2e94c |
| 08-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging qemu-sparc update # gpg: Signature made Thu 08 Mar 2018 07:23:01 GMT # gpg: us
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging qemu-sparc update # gpg: Signature made Thu 08 Mar 2018 07:23:01 GMT # gpg: using RSA key 5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: sparc: fix leon3 casa instruction when MMU is disabled hw/sparc/sun4m: Fix implicit creation of "-drive if=scsi" devices Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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6e10f37c |
| 02-Mar-2018 |
KONRAD Frederic <frederic.konrad@adacore.com> |
sparc: fix leon3 casa instruction when MMU is disabled Since the commit af7a06bac7d3abb2da48ef3277d2a415772d2ae8: `casa [..](10), .., ..` (and probably others alternate space instruction
sparc: fix leon3 casa instruction when MMU is disabled Since the commit af7a06bac7d3abb2da48ef3277d2a415772d2ae8: `casa [..](10), .., ..` (and probably others alternate space instructions) triggers a data access exception when the MMU is disabled. When we enter get_asi(...) dc->mem_idx is set to MMU_PHYS_IDX when the MMU is disabled. Just keep mem_idx unchanged in this case so we passthrough the MMU when it is disabled. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Revision tags: v2.11.1, ppc-for-2.12-20180212, ppc-for-2.12-20180129, ppc-for-2.12-20180121, ppc-for-2.12-20180119, ppc-for-2.12-20180117 |
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acc95bc8 |
| 11-Jan-2018 |
Michael S. Tsirkin <mst@redhat.com> |
Merge remote-tracking branch 'origin/master' into HEAD Resolve conflicts around apb. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Revision tags: ppc-for-2.12-20180111 |
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76302a95 |
| 09-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20180109-xtensa' into staging target/xtensa updates: - add libisa to the xtensa target; - change xtensa instruction translator
Merge remote-tracking branch 'remotes/xtensa/tags/20180109-xtensa' into staging target/xtensa updates: - add libisa to the xtensa target; - change xtensa instruction translator to use it; - switch existing xtensa cores to use it; - add support for a number of instructions: salt/saltu, const16, GPIO32 group, debug mode and MMU-related; - add disassembler for Xtensa. # gpg: Signature made Tue 09 Jan 2018 18:11:02 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180109-xtensa: target/xtensa: implement disassembler target/xtensa: implement const16 target/xtensa: implement GPIO32 target/xtensa: implement salt/saltu target/xtensa: add internal/noop SRs and opcodes target/xtensa: drop DisasContext::litbase target/xtensa: tests: fix memctl SR test target/xtensa: use libisa for instruction decoding target/xtensa: switch fsf to libisa target/xtensa: switch dc233c to libisa target/xtensa: switch dc232b to libisa target/xtensa: update import_core.sh script for libisa target/xtensa: extract FPU2000 opcode translators target/xtensa: extract core opcode translators target/xtensa: import libisa source target/xtensa: pass actual frame size to the entry helper Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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3cee4db6 |
| 09-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-01-08' into staging nbd patches for 2018-01-08 - Eric Blake: 0/2 Optimize sparse reads over NBD - Murilo Opsfelder
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-01-08' into staging nbd patches for 2018-01-08 - Eric Blake: 0/2 Optimize sparse reads over NBD - Murilo Opsfelder Araujo: block/nbd: fix segmentation fault when .desc is not null-terminated # gpg: Signature made Mon 08 Jan 2018 15:21:19 GMT # gpg: using RSA key 0xA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2018-01-08: block/nbd: fix segmentation fault when .desc is not null-terminated nbd/server: Optimize final chunk of sparse read nbd/server: Implement sparse reads atop structured reply Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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ee98a6b0 |
| 08-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging - Aneesh no longer listed in MAINTAINERS, - deprecation of the handle backend, - improved error reporting,
Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging - Aneesh no longer listed in MAINTAINERS, - deprecation of the handle backend, - improved error reporting, especially when the local backend fails to open the VirtFS root, - virtio-9p-test to behave more like a real virtio guest driver: set DRIVER_OK when ready to use the device and process the used ring for completed requests, - cosmetic fixes (mostly coding style related). # gpg: Signature made Mon 08 Jan 2018 10:19:18 GMT # gpg: using RSA key 0x71D4D5E5822F73D6 # gpg: Good signature from "Greg Kurz <groug@kaod.org>" # gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" # gpg: aka "[jpeg image of size 3330]" # Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6 * remotes/gkurz/tags/for-upstream: MAINTAINERS: Drop Aneesh as 9pfs maintainer 9pfs: deprecate handle backend fsdev: improve error handling of backend init fsdev: improve error handling of backend opts parsing tests: virtio-9p: set DRIVER_OK before using the device tests: virtio-9p: fix ISR dependence 9pfs: make pdu_marshal() and pdu_unmarshal() static functions 9pfs: fix error path in pdu_submit() 9pfs: fix type in *_parse_opts declarations 9pfs: handle: fix type definition 9pfs: fix some type definitions fsdev: fix some type definitions 9pfs: fix XattrOperations typedef virtio-9p: move unrealize/realize after virtio_9p_transport definition Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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232e5537 |
| 08-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Thu 04 Jan 2018 16:37:32 GMT # gpg: using RSA key 0xF30C38
Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Thu 04 Jan 2018 16:37:32 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: target/m68k: fix m68k_cpu_dump_state() target/m68k: add the Interrupt Stack Pointer target/m68k: add andi/ori/eori to SR/CCR target/m68k: add 680x0 "move to SR" instruction target/m68k: move CCR/SR functions target/m68k: implement fsave/frestore target/m68k: add reset target/m68k: add cpush/cinv target/m68k: softmmu cleanup target/m68k: add move16 target/m68k: add chk and chk2 target/m68k: manage 680x0 stack frames target/m68k: add CPU_LOG_INT trace target/m68k: use insn_pc to generate instruction fault address linux-user, m68k: correctly manage SR in context target/m68k: fix gen_get_ccr() target-m68k: sync CC_OP before gen_jmp_tb() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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4bd797af |
| 08-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/elmarco/tags/dump-pull-request' into staging # gpg: Signature made Tue 02 Jan 2018 13:51:26 GMT # gpg: using RSA key 0xDAE8E10975969C
Merge remote-tracking branch 'remotes/elmarco/tags/dump-pull-request' into staging # gpg: Signature made Tue 02 Jan 2018 13:51:26 GMT # gpg: using RSA key 0xDAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/dump-pull-request: dump-guest-memory.py: fix "You can't do that without a process to debug" dump: fix note_name_equal() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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4124ea4f |
| 08-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20171229' into staging Queued TCG patches # gpg: Signature made Fri 29 Dec 2017 20:44:06 GMT # gpg: using
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20171229' into staging Queued TCG patches # gpg: Signature made Fri 29 Dec 2017 20:44:06 GMT # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20171229: tcg: add cs_base and flags to -d exec output tcg: Allow 6 arguments to TCG helpers tcg: Add tcg_signed_cond tcg: Generalize TCGOp parameters tcg: Dynamically allocate TCGOps tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* target/moxie: Fix tlb_fill target/*helper: don't check retaddr before calling cpu_restore_state Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: ppc-for-2.12-20180108, ppc-for-2.12-20180103, ppc-for-2.12-20171219, v2.10.2, ppc-for-2.12-20171215, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, ppc-for-2.11-20171205, ppc-for-2.11-20171204, v2.11.0-rc3, ppc-for-2.11-20171127, ppc-for-2.11-20171122, v2.11.0-rc2, ppc-for-2.11-20171120, v2.11.0-rc1, ppc-for-2.11-20171114, ppc-for-2.11-20171108, v2.11.0-rc0 |
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f764718d |
| 02-Nov-2017 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* These are now trivial sets and tests against NULL. Unwrap. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Ric
tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* These are now trivial sets and tests against NULL. Unwrap. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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