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a648df38 |
| 28-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging # gpg: Signature made Thu 27 May 2021 04:06:17 BST # gpg: using RSA key EF04965B398D6211
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging # gpg: Signature made Thu 27 May 2021 04:06:17 BST # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * remotes/jasowang/tags/net-pull-request: tap-bsd: Remove special casing for older OpenBSD releases virtio-net: failover: add missing remove_migration_state_change_notifier() hw/net/imx_fec: return 0xffff when accessing non-existing PHY Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
62c0ac50 |
| 28-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into staging Adjust types for some memory access functions. Reduce inclusion of tcg headers. Fix watchpoints
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into staging Adjust types for some memory access functions. Reduce inclusion of tcg headers. Fix watchpoints vs replay. Fix tcg/aarch64 roli expansion. Introduce SysemuCPUOps structure. # gpg: Signature made Thu 27 May 2021 00:43:54 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210526: (31 commits) hw/core: Constify TCGCPUOps target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps cpu: Move CPUClass::write_elf* to SysemuCPUOps cpu: Move CPUClass::get_crash_info to SysemuCPUOps cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps cpu: Move CPUClass::vmsd to SysemuCPUOps cpu: Introduce SysemuCPUOps structure cpu: Move AVR target vmsd field from CPUClass to DeviceClass cpu: Rename CPUClass vmsd -> legacy_vmsd cpu: Assert DeviceClass::vmsd is NULL on user emulation cpu: Directly use get_memory_mapping() fallback handlers in place cpu: Directly use get_paging_enabled() fallback handlers in place cpu: Directly use cpu_write_elf*() fallback handlers in place cpu: Introduce cpu_virtio_is_big_endian() cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs cpu: Split as cpu-common / cpu-sysemu ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
11906557 |
| 27-Feb-2021 |
Richard Henderson <richard.henderson@linaro.org> |
hw/core: Constify TCGCPUOps We no longer have any runtime modifications to this struct, so declare them all const. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Review
hw/core: Constify TCGCPUOps We no longer have any runtime modifications to this struct, so declare them all const. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>
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#
08928c6d |
| 17-May-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-21-f4bug@amsat.org> [rth: Drop declaration movement from target/*/cpu.h] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
8b80bd28 |
| 17-May-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
cpu: Introduce SysemuCPUOps structure Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Hend
cpu: Introduce SysemuCPUOps structure Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-15-f4bug@amsat.org> [rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
78271684 |
| 04-Feb-2021 |
Claudio Fontana <cfontana@suse.de> |
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by bot
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
05456080 |
| 04-Feb-2021 |
Claudio Fontana <cfontana@suse.de> |
cpu: move cc->do_interrupt to tcg_ops Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.hend
cpu: move cc->do_interrupt to tcg_ops Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-10-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
e124536f |
| 04-Feb-2021 |
Eduardo Habkost <ehabkost@redhat.com> |
cpu: Move tlb_fill to tcg_ops [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de>
cpu: Move tlb_fill to tcg_ops [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-7-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
48c1a3e3 |
| 04-Feb-2021 |
Eduardo Habkost <ehabkost@redhat.com> |
cpu: Move cpu_exec_* to tcg_ops Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Claudio Fontana <cfontana@suse.de>
cpu: Move cpu_exec_* to tcg_ops Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-6-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
ec62595b |
| 04-Feb-2021 |
Eduardo Habkost <ehabkost@redhat.com> |
cpu: Move synchronize_from_tb() to tcg_ops Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG, reworded comments] Signed-off-by: Claudio
cpu: Move synchronize_from_tb() to tcg_ops Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG, reworded comments] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-5-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
e9e51b71 |
| 04-Feb-2021 |
Eduardo Habkost <ehabkost@redhat.com> |
cpu: Introduce TCGCpuOperations struct The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the
cpu: Introduce TCGCpuOperations struct The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded struct for now, to make code conversion easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: move TCGCpuOperations inside include/hw/core/cpu.h] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-2-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v5.2.0 |
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#
04a37d4c |
| 29-Oct-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Make tb arg to synchronize_from_tb const There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actual
tcg: Make tb arg to synchronize_from_tb const There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx region. Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
e4c4f7db |
| 07-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/hdeller/tags/target-hppa-pull-request' into staging hppa power button support, graphics updates and firmware fixes # gpg: Signature made Mon 07
Merge remote-tracking branch 'remotes/hdeller/tags/target-hppa-pull-request' into staging hppa power button support, graphics updates and firmware fixes # gpg: Signature made Mon 07 Sep 2020 20:09:49 BST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * remotes/hdeller/tags/target-hppa-pull-request: hw/display/artist: Allow screen size up to 2048 lines hw/display/artist: Refactor x/y coordination extraction hw/display/artist: Verify artist screen resolution target/hppa: Fix boot with old Linux installation CDs hw/hppa: Add power button emulation hw/hppa: Tell SeaBIOS port address of fw_cfg hw/hppa: Change fw_cfg port address hw/hppa: Store boot device in fw_cfg section hw/hppa: Make number of TLB and BTLB entries configurable seabios-hppa: Update SeaBIOS to hppa-qemu-5.2-2 tag Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
1133ce5e |
| 04-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging Add btrfs support Fix MK_ARRAY() # gpg: Signature made Thu 03 Sep 2020 00:26:37
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging Add btrfs support Fix MK_ARRAY() # gpg: Signature made Thu 03 Sep 2020 00:26:37 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-5.2-pull-request: linux-user: Add support for btrfs ioctls used to scrub a filesystem linux-user: Add support for btrfs ioctls used to manage quota linux-user: Add support for two btrfs ioctls used for subvolume linux-user: Add support for a group of btrfs inode ioctls linux-user: Add support for btrfs ioctls used to get/set features linux-user: Add support for btrfs ioctls used to manipulate with devices linux-user: Add support for a group of btrfs ioctls used for snapshots linux-user: Add support for a group of btrfs ioctls used for subvolumes linux-user: fix implicit conversion from enumeration type error Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
3dd23a4f |
| 03-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200901' into staging Various fixes of Aspeed machines : * New Supermicro X11 BMC machine (Erik) * Fixed valid a
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200901' into staging Various fixes of Aspeed machines : * New Supermicro X11 BMC machine (Erik) * Fixed valid access size on AST2400 SCU * Improved robustness of the ftgmac100 model. * New flash models in m25p80 (Igor) * Fixed reset sequence of SDHCI/eMMC controllers * Improved support of the AST2600 SDMC (Joel) * Couple of SMC cleanups # gpg: Signature made Tue 01 Sep 2020 13:39:20 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20200901: hw: add a number of SPI-flash's of m25p80 family arm: aspeed: add strap define `25HZ` of AST2500 aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller aspeed/sdmc: Simplify calculation of RAM bits aspeed/sdmc: Allow writes to unprotected registers aspeed/sdmc: Perform memory training ftgmac100: Improve software reset ftgmac100: Fix integer overflow in ftgmac100_do_tx() ftgmac100: Check for invalid len and address before doing a DMA transfer ftgmac100: Change interrupt status when a DMA error occurs ftgmac100: Fix interrupt status "Packet moved to RX FIFO" ftgmac100: Fix interrupt status "Packet transmitted on ethernet" ftgmac100: Fix registers that can be read aspeed/sdhci: Fix reset sequence aspeed/smc: Fix max_slaves of the legacy SMC device aspeed/smc: Fix MemoryRegionOps definition hw/arm/aspeed: Add board model for Supermicro X11 BMC aspeed/scu: Fix valid access size on AST2400 m25p80: Add support for n25q512ax3 m25p80: Return the JEDEC ID twice for mx25l25635e Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
e4d8b7c1 |
| 02-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/nvme/tags/pull-nvme-20200902' into staging qemu-nvme # gpg: Signature made Wed 02 Sep 2020 15:39:10 BST # gpg: using RSA key
Merge remote-tracking branch 'remotes/nvme/tags/pull-nvme-20200902' into staging qemu-nvme # gpg: Signature made Wed 02 Sep 2020 15:39:10 BST # gpg: using RSA key DBC11D2D373B4A3755F502EC625156610A4F6CC0 # gpg: Good signature from "Keith Busch <kbusch@kernel.org>" [unknown] # gpg: aka "Keith Busch <keith.busch@gmail.com>" [unknown] # gpg: aka "Keith Busch <keith.busch@intel.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DBC1 1D2D 373B 4A37 55F5 02EC 6251 5661 0A4F 6CC0 * remotes/nvme/tags/pull-nvme-20200902: (39 commits) hw/block/nvme: remove explicit qsg/iov parameters hw/block/nvme: use preallocated qsg/iov in nvme_dma_prp hw/block/nvme: consolidate qsg/iov clearing hw/block/nvme: add ns/cmd references in NvmeRequest hw/block/nvme: be consistent about zeros vs zeroes hw/block/nvme: add check for mdts hw/block/nvme: refactor request bounds checking hw/block/nvme: verify validity of prp lists in the cmb hw/block/nvme: add request mapping helper hw/block/nvme: add tracing to nvme_map_prp hw/block/nvme: refactor dma read/write hw/block/nvme: destroy request iov before reuse hw/block/nvme: remove redundant has_sg member hw/block/nvme: replace dma_acct with blk_acct equivalent hw/block/nvme: add mapping helpers hw/block/nvme: memset preallocated requests structures hw/block/nvme: bump supported version to v1.3 hw/block/nvme: provide the mandatory subnqn field hw/block/nvme: enforce valid queue creation sequence hw/block/nvme: reject invalid nsid values in active namespace id list ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
ed215cec |
| 02-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging x86 and machine queue, 2020-09-02 Bug fixes: * Revert EPYC topology patches that caus
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging x86 and machine queue, 2020-09-02 Bug fixes: * Revert EPYC topology patches that caused regressions (Babu Moger) * Memory leak fixes (Pan Nengyuan) QOM Cleanups: * Fix typo in AARCH64_CPU_GET_CLASS * Rename QOM macros for consistency and/or to avoid conflicts with other symbols * Move typedefs to header files * Correct instance/class sizes # gpg: Signature made Wed 02 Sep 2020 12:49:57 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/machine-next-pull-request: target/i386/sev: Plug memleak in sev_read_file_base64 target/i386/cpu: Fix memleak in x86_cpu_class_check_missing_features virtio: add Virtio*BusClass sizes Revert "hw/i386: Update structures to save the number of nodes per package" Revert "hw/386: Add EPYC mode topology decoding functions" Revert "target/i386: Cleanup and use the EPYC mode topology functions" Revert "hw/i386: Introduce apicid functions inside X86MachineState" Revert "i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition" Revert "hw/i386: Move arch_id decode inside x86_cpus_init" Revert "target/i386: Enable new apic id encoding for EPYC based cpus models" Revert "i386: Fix pkg_id offset for EPYC cpu models" tls-cipher-suites: Correct instance_size hda-audio: Set instance_size at base class rx: Move typedef RXCPU to cpu-qom.h rx: Rename QOM type check macros arm: Fix typo in AARCH64_CPU_GET_CLASS definition rdma: Rename INTERFACE_RDMA_PROVIDER_CLASS macro x86-iommu: Rename QOM type macros mos6522: Rename QOM macros imx_ccm: Rename IMX_GET_CLASS macro Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
38688fdb |
| 25-Aug-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
rx: Rename QOM type check macros Currently we have a RXCPU typedef and a RXCPU type checking macro, but OBJECT_DECLARE* would transform the RXCPU macro into a function, and the funct
rx: Rename QOM type check macros Currently we have a RXCPU typedef and a RXCPU type checking macro, but OBJECT_DECLARE* would transform the RXCPU macro into a function, and the function name would conflict with the typedef name. Rename the RXCPU* QOM type check macros to RX_CPU*, so we will avoid the conflict and make the macro names consistent with the TYPE_RX_CPU constant name. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-53-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Revision tags: v5.0.0 |
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#
29e0855c |
| 22-Mar-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/elmarco/tags/slirp-pull-request' into staging # gpg: Signature made Sun 22 Mar 2020 17:07:31 GMT # gpg: using RSA key 87A9BD933F87C60
Merge remote-tracking branch 'remotes/elmarco/tags/slirp-pull-request' into staging # gpg: Signature made Sun 22 Mar 2020 17:07:31 GMT # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full] # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/slirp-pull-request: slirp: update submodule to v4.2.0+ Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
52a96afa |
| 20-Mar-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging update syscall numbers to linux 5.5 (with scripts) add clock_gettime64/clock_settime64
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging update syscall numbers to linux 5.5 (with scripts) add clock_gettime64/clock_settime64 add AT_EXECFN v4: restore syscall.tbl series but remove vsyscall series v3: remove syscall.tbl series v2: guard copy_to_user_timezone() with TARGET_NR_gettimeofday remove "Support futex_time64" patch guard sys_futex with TARGET_NR_exit # gpg: Signature made Fri 20 Mar 2020 15:23:29 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-5.0-pull-request: (32 commits) linux-user, openrisc: sync syscall numbers with kernel v5.5 linux-user, nios2: sync syscall numbers with kernel v5.5 linux-user, aarch64: sync syscall numbers with kernel v5.5 scripts: add a script to generate syscall_nr.h linux-user,mips: update syscall-args-o32.c.inc linux-user,mips: move content of mips_syscall_args linux-user: update syscall.tbl from linux 0bf999f9c5e7 linux-user, scripts: add a script to update syscall.tbl linux-user, mips64: add syscall table generation support linux-user, mips: add syscall table generation support linux-user, x86_64: add syscall table generation support linux-user, i386: add syscall table generation support linux-user, x86_64, i386: cleanup TARGET_NR_arch_prctl linux-user, sparc, sparc64: add syscall table generation support linux-user, s390x: add syscall table generation support linux-user, s390x: remove syscall definitions for !TARGET_S390X linux-user, ppc: add syscall table generation support linux-user, arm: add syscall table generation support linux-user, microblaze: add syscall table generation support linux-user, sh4: add syscall table generation support ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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3d0ac346 |
| 20-Mar-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging Python queue for 5.0 soft freeze * Add scripts/simplebench (Vladimir Sementsov-Ogievskiy)
Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request' into staging Python queue for 5.0 soft freeze * Add scripts/simplebench (Vladimir Sementsov-Ogievskiy) # gpg: Signature made Wed 18 Mar 2020 01:11:49 GMT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/python-next-pull-request: MAINTAINERS: add simplebench scripts/simplebench: add example usage of simplebench scripts/simplebench: add qemu/bench_block_job.py scripts/simplebench: add simplebench.py Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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226cd207 |
| 20-Mar-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/target_renesas_rx-20200320' into staging Introduce the architectural part of the Renesas RX architecture emulation, developed by
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/target_renesas_rx-20200320' into staging Introduce the architectural part of the Renesas RX architecture emulation, developed by Yoshinori Sato. CI jobs results: https://gitlab.com/philmd/qemu/pipelines/127886344 https://travis-ci.org/github/philmd/qemu/builds/664579420 # gpg: Signature made Fri 20 Mar 2020 10:27:32 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/target_renesas_rx-20200320: Add rx-softmmu target/rx: Dump bytes for each insn during disassembly target/rx: Collect all bytes during disassembly target/rx: Emit all disassembly in one prt() target/rx: Use prt_ldmi for XCHG_mr disassembly target/rx: Replace operand with prt_ldmi in disassembler target/rx: Disassemble rx_index_addr into a string target/rx: RX disassembler target/rx: CPU definitions target/rx: TCG helpers target/rx: TCG translation MAINTAINERS: Add entry for the Renesas RX architecture hw/registerfields.h: Add 8bit and 16bit register macros Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v4.2.0, v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
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27a4a30e |
| 21-Jan-2019 |
Yoshinori Sato <ysato@users.sourceforge.jp> |
target/rx: CPU definitions Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson <
target/rx: CPU definitions Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use newer QOM style, split cpu-qom.h, restrict access to extable array, use rx_cpu_tlb_fill() extracted from patch of Yoshinori Sato 'Convert to CPUClass::tlb_fill', call cpu_reset after qemu_init_vcpu, make rx_crname a function] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20200224141923.82118-7-ysato@users.sourceforge.jp> Acked-by: Richard Henderson <richard.henderson@linaro.org> [PMD: Use GByteArray in gdbstub (rebase commit a010bdbe), use device_class_set_parent_reset (rebase commit 781c67ca)] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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