#
e6a5ad43 |
| 06-Jun-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: use int128.h methods in vsubecuq and vsubeuqm
And also move the insns to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.col
target/ppc: use int128.h methods in vsubecuq and vsubeuqm
And also move the insns to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220606150037.338931-7-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
b132be53 |
| 06-Jun-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: use int128.h methods in vsubuqm
And also move the insn to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.or
target/ppc: use int128.h methods in vsubuqm
And also move the insn to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220606150037.338931-6-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
8290ea50 |
| 06-Jun-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: use int128.h methods in vaddcuq
And also move the insn to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.o
target/ppc: use int128.h methods in vaddcuq
And also move the insn to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220606150037.338931-5-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
896d92c8 |
| 06-Jun-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: use int128.h methods in vaddecuq and vaddeuqm
And also move the insns to decodetree and remove the now unused avr_qw_addc method.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.or
target/ppc: use int128.h methods in vaddecuq and vaddeuqm
And also move the insns to decodetree and remove the now unused avr_qw_addc method.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220606150037.338931-4-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
7ca04286 |
| 06-Jun-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: use int128.h methods in vadduqm
And also move the insn to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.o
target/ppc: use int128.h methods in vadduqm
And also move the insn to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220606150037.338931-3-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
e82ca8ac |
| 06-Jun-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: use int128.h methods in vpmsumd
Also drop VECTOR_FOR_INORDER_I usage since there is no need to access the elements in any particular order, and move the instruction to decodetree.
Signe
target/ppc: use int128.h methods in vpmsumd
Also drop VECTOR_FOR_INORDER_I usage since there is no need to access the elements in any particular order, and move the instruction to decodetree.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220606150037.338931-2-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
feeef6b6 |
| 02-Jun-2022 |
Daniel Henrique Barboza <danielhb413@gmail.com> |
target/ppc: avoid int32 multiply overflow in int_helper.c
Coverity is not thrilled about the multiply operations being done in ger_rank8() and ger_rank2(), giving an error like the following:
Integ
target/ppc: avoid int32 multiply overflow in int_helper.c
Coverity is not thrilled about the multiply operations being done in ger_rank8() and ger_rank2(), giving an error like the following:
Integer handling issues (OVERFLOW_BEFORE_WIDEN) Potentially overflowing expression "sextract32(a, 4 * i, 4) * sextract32(b, 4 * i, 4)" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "int64_t" (64 bits, signed).
Fix both instances where this occur by adding an int64_t cast in the first operand, forcing the result to be 64 bit.
Fixes: Coverity CID 1489444, 1489443 Fixes: 345531533f26 ("target/ppc: Implemented xvi*ger* instructions") Cc: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Cc: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20220602141449.118173-1-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
8f7d41e0 |
| 01-Jun-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: fix vbpermd in big endian hosts
The extract64 arguments are not endian dependent as they are only used for bitwise operations. The current behavior in little-endian hosts is correct; sin
target/ppc: fix vbpermd in big endian hosts
The extract64 arguments are not endian dependent as they are only used for bitwise operations. The current behavior in little-endian hosts is correct; since the indexes in VRB are in PowerISA-ordering, we should always invert the value before calling extract64. Also, using the VsrD macro, we can have a single EXTRACT_BIT definition for big and little-endian with the correct behavior.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220601125355.1266165-1-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
b80bec3a |
| 25-May-2022 |
Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> |
target/ppc: Implemented vector module quadword
Implement the following PowerISA v3.1 instructions: vmodsq: Vector Modulo Signed Quadword vmoduq: Vector Modulo Unsigned Quadword
Signed-off-by: Lucas
target/ppc: Implemented vector module quadword
Implement the following PowerISA v3.1 instructions: vmodsq: Vector Modulo Signed Quadword vmoduq: Vector Modulo Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/744 Message-Id: <20220525134954.85056-9-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
a173ba88 |
| 25-May-2022 |
Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> |
target/ppc: Implemented remaining vector divide extended
Implement the following PowerISA v3.1 instructions: vdivesd: Vector Divide Extended Signed Doubleword vdiveud: Vector Divide Extended Unsigne
target/ppc: Implemented remaining vector divide extended
Implement the following PowerISA v3.1 instructions: vdivesd: Vector Divide Extended Signed Doubleword vdiveud: Vector Divide Extended Unsigned Doubleword vdivesq: Vector Divide Extended Signed Quadword vdiveuq: Vector Divide Extended Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-7-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
1700f2bf |
| 25-May-2022 |
Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> |
target/ppc: Implemented vector divide quadword
Implement the following PowerISA v3.1 instructions: vdivsq: Vector Divide Signed Quadword vdivuq: Vector Divide Unsigned Quadword
Signed-off-by: Lucas
target/ppc: Implemented vector divide quadword
Implement the following PowerISA v3.1 instructions: vdivsq: Vector Divide Signed Quadword vdivuq: Vector Divide Unsigned Quadword
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-3-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
34553153 |
| 24-May-2022 |
Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> |
target/ppc: Implemented xvi*ger* instructions
Implement the following PowerISA v3.1 instructions: xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) xvi4ger8pp: VSX Vector
target/ppc: Implemented xvi*ger* instructions
Implement the following PowerISA v3.1 instructions: xvi4ger8: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) xvi4ger8pp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate xvi8ger4: VSX Vector 4-bit Signed Integer GER (rank-8 update) xvi8ger4pp: VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate xvi8ger4spp: VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate xvi16ger2: VSX Vector 16-bit Signed Integer GER (rank-2 update) xvi16ger2pp: VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate xvi16ger2s: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation xvi16ger2spp: VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220524140537.27451-3-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
6f52f731 |
| 17-May-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: declare vmsumsh[ms] helper with call flags
Move vmsumshm and vmsumshs to decodetree, declare vmsumshm helper with TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Mathe
target/ppc: declare vmsumsh[ms] helper with call flags
Move vmsumshm and vmsumshs to decodetree, declare vmsumshm helper with TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220517123929.284511-13-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
89a5a1ae |
| 17-May-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: declare vmsumuh[ms] helper with call flags
Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Mathe
target/ppc: declare vmsumuh[ms] helper with call flags
Move vmsumuhm and vmsumuhs to decodetree, declare vmsumuhm helper with TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220517123929.284511-12-matheus.ferst@eldorado.org.br> [danielhb: added #undef VMSUMUHM to fix ppc64 build] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
b2dc03a5 |
| 17-May-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: declare vmsum[um]bm helpers with call flags
Move vmsumubm and vmsummbm to decodetree, declare both helpers with TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus
target/ppc: declare vmsum[um]bm helpers with call flags
Move vmsumubm and vmsummbm to decodetree, declare both helpers with TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220517123929.284511-11-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
8f5eeee3 |
| 17-May-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: declare xxextractuw and xxinsertw helpers with call flags
Move xxextractuw and xxinsertw to decodetree, declare both helpers with TCG_CALL_NO_RWG, and drop the unused env argument.
Sign
target/ppc: declare xxextractuw and xxinsertw helpers with call flags
Move xxextractuw and xxinsertw to decodetree, declare both helpers with TCG_CALL_NO_RWG, and drop the unused env argument.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220517123929.284511-9-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Revision tags: v7.0.0 |
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#
e03b5686 |
| 23-Mar-2022 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
Replace config-time define HOST_WORDS_BIGENDIAN
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoid
Replace config-time define HOST_WORDS_BIGENDIAN
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before.
This can help to make some code independent from qemu too.
gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
618574dd |
| 05-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: split XXGENPCV macros for readability
Fixes: b090f4f1e3c9 ("target/ppc: Implement xxgenpcv[bhwd]m instruction") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by:
target/ppc: split XXGENPCV macros for readability
Fixes: b090f4f1e3c9 ("target/ppc: Implement xxgenpcv[bhwd]m instruction") Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220304175156.2012315-6-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
b090f4f1 |
| 01-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: Implement xxgenpcv[bhwd]m instruction
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <202202252109
target/ppc: Implement xxgenpcv[bhwd]m instruction
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225210936.1749575-36-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
1015fcab |
| 01-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: Implement xxeval
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225210936.1749575-35-matheus
target/ppc: Implement xxeval
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225210936.1749575-35-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
41c2877f |
| 01-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: Implement xxpermx instruction
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.17495
target/ppc: Implement xxpermx instruction
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-33-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
28347fe2 |
| 01-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: Move vsel and vperm/vpermr to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <202202252
target/ppc: Move vsel and vperm/vpermr to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-29-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
02c74f0e |
| 01-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <2022022
target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220225210936.1749575-25-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
fb5303cc |
| 01-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: implement vstri[bh][lr]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-15-
target/ppc: implement vstri[bh][lr]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-15-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
eb936dc0 |
| 01-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
target/ppc: Move Vector Compare Not Equal or Zero to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id:
target/ppc: Move Vector Compare Not Equal or Zero to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220225210936.1749575-11-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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