#
4a52ef61 |
| 06-Jun-2023 |
qianfan Zhao <qianfanguijin@163.com> |
hw/arm/allwinner-r40: add SDRAM controller device
Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner R
hw/arm/allwinner-r40: add SDRAM controller device
Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner R40 SDRAM controller.
This driver only support 256M, 512M and 1024M memory now.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
a9545430 |
| 06-Jun-2023 |
qianfan Zhao <qianfanguijin@163.com> |
hw/misc: Rename axp209 to axp22x and add support AXP221 PMU
This patch adds minimal support for AXP-221 PMU and connect it to bananapi M2U board.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
hw/misc: Rename axp209 to axp22x and add support AXP221 PMU
This patch adds minimal support for AXP-221 PMU and connect it to bananapi M2U board.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
17159fbb |
| 13-Apr-2023 |
Joe Komlodi <komlodi@google.com> |
hw/misc/aspeed_i3c: Move to i3c directory
Moves the Aspeed I3C model and traces into hw/i3c and create I3C build files.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture
hw/misc/aspeed_i3c: Move to i3c directory
Moves the Aspeed I3C model and traces into hw/i3c and create I3C build files.
Signed-off-by: Joe Komlodi <komlodi@google.com>
Reviewed-by: Patrick Venture <venture@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
10c93af3 |
| 13-Apr-2023 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to communicate with an external PowerNV machine. It uses the OpenIPMI simulator protocol for virtual mac
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to communicate with an external PowerNV machine. It uses the OpenIPMI simulator protocol for virtual machines described in :
https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
and implemented by the 'ipmi-bmc-extern' model on the host side.
To use, start the Aspeed BMC machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \ -global driver=aspeed.ibt,property=chardev,value=ipmi0
and the PowerNV machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \ -device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \ -device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults
Cc: Hao Wu <wuhaotsh@google.com> Cc: Corey Minyard <cminyard@mvista.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210407171637.777743-20-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
088484e2 |
| 13-Apr-2023 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add basic Aspeed PWM model
Just enough to quiet down the output when running with the logs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
1b3529e7 |
| 13-Apr-2023 |
Joel Stanley <joel@jms.id.au> |
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.
hw/misc: Add basic Aspeed GFX model
Enough model to capture the pinmux writes to enable correct operation of the parts of pinmux that depend on GFX registers.
Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20230119124440.50243-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
886fb670 |
| 13-Jan-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: hw/arm/stm32f405: correctly describe the memory layout hw/arm: Add Olimex H40
Merge tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: hw/arm/stm32f405: correctly describe the memory layout hw/arm: Add Olimex H405 board cubieboard: Support booting from an SD card image with u-boot on it target/arm: Fix sve_probe_page target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled various code cleanups
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmPBZmYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3rDdD/9GlrH14yP/2WQZJVJxzXkf # ltO1pvX/AfeNPGy3F8T+kncKspIUeJ8BQNrZKYPWkH1WgAAT3lVH/cUbAlr8UD6W # p2t64ZdQAURuEw3kqtyUVOUeIxzg29cEQyW/9uchA3QPb9xDtiq6KLpAzifDzo6o # 2JE4/NytUJSKxFr5hnyxRTtOYPEMLShBSPvPzU0/BPq7VPyPhT4rqojhpx9uZpVc # h4mfVm9cpF0y3ThBR37M0nhEGJywB/6zOsZ49bm06MFFTwasZ4P0w0fcKhbvrFvX # PHVlNOvyT1oxch5ErN+KULZLByiWy0/Nw85V8P9R+1hU6nncQPM5paB6Y5HUCTKv # wa9gp38V8323fsHg2EEV/PYRdcmRWSBHOq9HPDjIIJlG9nvfXn9O69kDlhnst44b # Fz27XiGJOKY+f20l0J0KzaOnnjw54aeo5tc5WUDbBiZ/btsAHBGQAg7JghmoLkhb # rlvJFgGdG99IuBqJH69dJQ8n/R9bGDRu6X0i1ir3d3C2nY9HYaWUZMyyxOw9dV43 # igQHupOzyYbSyy9+40xz611P0h2k2d90P61Vi41D9ig4Du+I4Vftjqj9mi/Z829k # W1JE5wpKWcDeIXFYLWCZuiOyTCCFBWiWgDJz/zQf7AYma0AWA9gpKrTh2+3EFfqy # VsvMR2T6kmS3FId50bW5OQ== # =D+ib # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Jan 2023 14:10:46 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm: (38 commits) target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock' hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic' hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE() hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name hw/arm/stellaris: Drop useless casts from void * to pointer hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name hw/arm/omap: Drop useless casts from void * to pointer hw/gpio/omap_gpio: Add local variable to avoid embedded cast hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState hw/arm: Remove unreachable code calling pflash_cfi01_register() hw/arm/vexpress: Remove dead code in vexpress_common_init() hw/arm/z2: Use the IEC binary prefix definitions hw/arm/omap_sx1: Use the IEC binary prefix definitions hw/arm/omap_sx1: Remove unused 'total_ram' definitions ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
632dfea3 |
| 26-Dec-2022 |
Strahinja Jankovic <strahinjapjankovic@gmail.com> |
hw/misc: AXP209 PMU Emulation
This patch adds minimal support for AXP-209 PMU. Most important is chip ID since U-Boot SPL expects version 0x1. Besides the chip ID register, reset values for two more
hw/misc: AXP209 PMU Emulation
This patch adds minimal support for AXP-209 PMU. Most important is chip ID since U-Boot SPL expects version 0x1. Besides the chip ID register, reset values for two more registers used by A10 U-Boot SPL are covered.
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20221226220303.14420-5-strahinja.p.jankovic@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
81bdacb6 |
| 05-Dec-2022 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to communicate with an external PowerNV machine. It uses the OpenIPMI simulator protocol for virtual mac
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to communicate with an external PowerNV machine. It uses the OpenIPMI simulator protocol for virtual machines described in :
https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
and implemented by the 'ipmi-bmc-extern' model on the host side.
To use, start the Aspeed BMC machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \ -global driver=aspeed.ibt,property=chardev,value=ipmi0
and the PowerNV machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \ -device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \ -device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults
Cc: Hao Wu <wuhaotsh@google.com> Cc: Corey Minyard <cminyard@mvista.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210407171637.777743-20-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
c9f82360 |
| 05-Dec-2022 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add basic Aspeed PWM model
Just enough to quiet down the output when running with the logs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
#
7b06148d |
| 08-Aug-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'mips-20220809' of https://github.com/philmd/qemu into staging
MIPS/SPARC patches queue
- target/mips: Handle lock_user failure in UHI_plog semihosting (Peter Maydell) - hw/mips/malta: Tu
Merge tag 'mips-20220809' of https://github.com/philmd/qemu into staging
MIPS/SPARC patches queue
- target/mips: Handle lock_user failure in UHI_plog semihosting (Peter Maydell) - hw/mips/malta: Turn off x86 specific features of PIIX4 PM (Igor Mammedov) - hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses (Peter Maydell)
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmLxjkMACgkQ4+MsLN6t # wN4DhQ/+L/lcVmz/hoIDsjyqMBpBYMYEftlytyuXUDqp9+1CGQpXXzf6cmXwiMK5 # DDP/q0PR508tevljDuc7A01ThkN5Vx8FcEpCaD54AjZ5n0BxSLl0Yw9Leftq8doD # Nk0YonVEY1tNXYV/KGWsiA7Xhkm3pL66Jzc0fyotNhzsI/dGxTVO9vLTgLl4/Hxv # iMj0AxPIOrKEsom61k6QKLgE5ZC3yIPZb+6upSwrQfx6oMtIac5NofEjNCuR0Uy5 # PgM6ZJKAM376JlP4hdJ91K04Wg8ql+ze/x2jpjbR0S3QRz4TbH57hJ00nNRLxDep # 5hHE7FIg6xf7sJv8ukwLK31zOiT46Azkr1wG97mZ7NyxxT7VTXtKgje6IENLGCgy # sCMWIEnrOh03seMShaCRqPcguYUR+XaMc+Hpv9XCu3ZvniI2CUpmVlm8M0t3hqVK # XCMwSsXJZ2w4522lUAJio2a10dsHJDg8U81n1KozTRUEZ8QBVlkqNLAIsROKl1Fr # LMsv9408nQLkAhYCBeZArw8ayITLTPqlE/S7fiLwwa6e8lPpkMyz/RlN16QsCSHr # zQO0iwY4kldn7QekKPTMQE73sW5ziBIOe7P6F5jtexbeaY0vJ5ph8Kfrq6hUVuqN # ieQVSi4psz43fpIjNodTk0nnsqAJXZ/7vy0sS38DvwQjBZojWIk= # =RIZd # -----END PGP SIGNATURE----- # gpg: Signature made Mon 08 Aug 2022 03:29:23 PM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
* tag 'mips-20220809' of https://github.com/philmd/qemu: hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses hw/mips/malta: turn off x86 specific features of PIIX4_PM target/mips: Handle lock_user() failure in UHI_plog semihosting call
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
09d12c81 |
| 02-Aug-2022 |
Peter Maydell <peter.maydell@linaro.org> |
hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses
In real hardware, the APB and AHB PNP data tables can be accessed with byte and halfword reads as well as word reads. Our implementation cur
hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses
In real hardware, the APB and AHB PNP data tables can be accessed with byte and halfword reads as well as word reads. Our implementation currently only handles word reads. Add support for the 8 and 16 bit accesses. Note that we only need to handle aligned accesses -- unaligned accesses should continue to trap, as happens on hardware.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1132 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Message-Id: <20220802131925.3380923-1-peter.maydell@linaro.org> Tested-by: Tomasz Martyniak <gitlab.com/tom4r> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
d495e432 |
| 30-Jun-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging
aspeed queue:
* m25p80 improvements (Iris) * Code cleanup in preparation of multi SoC machine (Peter) * New MAX3178
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into staging
aspeed queue:
* m25p80 improvements (Iris) * Code cleanup in preparation of multi SoC machine (Peter) * New MAX31785 model (Mahesh) * New Qualcomm machines (Jae and Graeme) * Core I2C slave mode (Klaus) * Aspeed I2C slave mode for old and new register interface (Peter and Klaus) * New Aspeed PECI model (Peter) * Various small fixes
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmK9UfQACgkQUaNDx8/7 # 7KFYWhAAtlx3aaEacrn/ONNHjk6G9Fxku56gAbaIiuiaIWNOj3/T2frPsnmbO8x8 # EKrgUYB8i8PFve/fJYA5vZUzIddPTaHkULZ12JQoGVg0L9hDBbizslN5lJWRXoSv # 9r3DF9nahzLKRNvzoBfuKjHDQ2cwHoFgYmKmlYpDcgfmBcl16uzZy8jvxg/Tghur # umH4IJMjeDNz/kLfINoO/m+kuFPVXmbTJNwl8uK5MUVDTgVSqharywWlUizugBVH # StLE+GmBPylTuYXyiOzLTkoGJeeHp3sQ1DmyI4DD83odjnfxa0BGMGDVhD35exXi # 9tLY9FgQ4smATuyN0UGAKZTBmzpI+ov0HMzvH4lUMR8i8daBuEet3RVr/DqkOP4h # LEVTRWTaTJip24ohgw4K/b86pI9nTJWVPGV56eZGYmnqufnvf/upNU65/nCsF/xD # i1TdS+zJWxhjgGEepg9cTmxxUlA4jVNNbl6dvAgS5Jr6Igrd1BlCSXjmyhO3NRPZ # bgOuvCb3RyxAY4+/9wphx2/t5X2VIU6R8EAjnh+7nIgBhOQU5SZ6uefFVYZq8xx+ # IYEDHj3saiRa4FHmyOgeRxRaQj/Vvs83PPti2rPmJuieqiClJmbE+XfTIamoxVIv # 5USlKmMRRVI69MjsjwFi/gOaV/N1EUgcFoYbnvwZ+Md3fg5+70M= # =oUKu # -----END PGP SIGNATURE----- # gpg: Signature made Thu 30 Jun 2022 01:04:12 PM +0530 # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu: (27 commits) hw/misc/aspeed: Add PECI controller hw/i2c/aspeed: Add new-registers DMA slave mode RX support hw/i2c/aspeed: add slave device in old register mode hw/i2c: add asynchronous send hw/i2c: support multiple masters hw/i2c/aspeed: Fix MASTER_EN missing error message hw/i2c/aspeed: Fix DMA len write-enable bit handling hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference hw/arm/aspeed: firework: add I2C MUXes for VR channels hw/arm/aspeed: firework: Add Thermal Diodes hw/arm/aspeed: Add MAX31785 Fan controllers hw/sensor: add Maxim MAX31785 device hw/i2c: pmbus: Page #255 is valid page for read requests. hw/arm/aspeed: add Qualcomm Firework BMC machine hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board aspeed: Remove use of qemu_get_cpu aspeed: Map unimplemented devices in SoC memory aspeed: Remove usage of sysbus_mmio_map aspeed: Add memory property to Aspeed SoC aspeed: Set CPU memory property explicitly ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
55c57023 |
| 30-Jun-2022 |
Peter Delevoryas <pdel@fb.com> |
hw/misc/aspeed: Add PECI controller
This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate
hw/misc/aspeed: Add PECI controller
This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate the command is done. This helps avoid getting hit with constant errors if the driver continuously attempts to send a command and keeps timing out.
The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC. They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support PECI 4.0, which includes more read/write buffer registers from 0x80 to 0xFC to support 64-byte mode.
This patch doesn't attempt to handle that, or to create a different version of the controller for the different generations, since it's only implementing functionality that is common to all generations.
The basic sequence of events is that the firmware will read and write to various registers and then trigger a command by setting the FIRE bit in the command register (similar to the I2C controller).
Then the firmware waits for an interrupt from the PECI controller, expecting the interrupt status register to be filled in with info on what happened. If the command was transmitted and received successfully, then response codes from the host CPU will be found in the data buffer registers.
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-12-me@pjd.dev> [ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
673a6d16 |
| 30-Jun-2022 |
Cédric Le Goater <clg@kaod.org> |
aspeed/scu: Add trace events for read ops
Reviewed-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220628154740.1117349-2-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
55462322 |
| 08-May-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging
qemu-sparc queue
# -----BEGIN PGP SIGNATURE----- # # iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmJ4A6ceHG1hcmsuY2F
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging
qemu-sparc queue
# -----BEGIN PGP SIGNATURE----- # # iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmJ4A6ceHG1hcmsuY2F2 # ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIf4SAH+weljMrdObceJ4vg # MedvVXUGmr0Uzk0iSkac1FGLCwEC/9bzBMrxMxNCsGHwVWjuX7S9Vikj/4mMi15U # 6iJ56QzVbsxZknr2+gGtB4QEAWHlQSuSrvcFVFc+Vc9enCBZNZoaehF0HzUSUFxU # nMnZQqDWrc4H9D2E+YK4OLgv3IMqOy3uKWMgIZ7JJX6YebLMXqZV1mq2G9LjKf9X # zM3HM6V9yd+1UEzb5biHkorBcdyt5F8P/V1VtiGZYFws27UwSBxW9EEDV3XcSGYD # kS9RpYka4qmC0saj5cBUR/AYQ/jwSbI9kEs4VsBzRQ/eX25F5TPEbyXp6bJZ75Gi # tsOhvvg= # =Qnnm # -----END PGP SIGNATURE----- # gpg: Signature made Sun 08 May 2022 12:53:43 PM CDT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu: (53 commits) artist: only render dirty scanlines on the display surface artist: remove unused ROP8OFF() macro artist: checkpatch and newline style fixes hppa: simplify machine function names in machine.c hppa: fold machine_hppa_machine_init() into machine_hppa_machine_init_class_init() hppa: use MACHINE QOM macros for defining the hppa machine hppa: remove the empty hppa_sys.h file hppa: move enable_lan() define from hppa_sys.h to machine.c hppa: remove unused trace-events from from hw/hppa hppa: remove hw/hppa/pci.c hppa: move hppa_pci_ignore_ops from pci.c to machine.c lasi: move from hw/hppa to hw/misc hppa: move device headers from hppa_sys.h into individual .c files lasi: use numerical constant for iar reset value lasi: use constants for device register offsets lasi: move lasi_initfn() to machine.c lasi: remove address space parameter from lasi_initfn() lasi: move PS2 initialisation to machine.c lasi: move second serial port initialisation to machine.c lasi: move parallel port initialisation to machine.c ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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45f569a1 |
| 04-May-2022 |
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
lasi: move from hw/hppa to hw/misc
Move the LASI device implementation from hw/hppa to hw/misc so that it is located with all the other miscellaneous devices.
Signed-off-by: Mark Cave-Ayland <mark.
lasi: move from hw/hppa to hw/misc
Move the LASI device implementation from hw/hppa to hw/misc so that it is located with all the other miscellaneous devices.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220504092600.10048-43-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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f6df0268 |
| 20-Apr-2022 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to communicate with an external PowerNV machine. It uses the OpenIPMI simulator protocol for virtual mac
hw/misc: Add an iBT device model
Implement an IPMI BT interface model using a chardev backend to communicate with an external PowerNV machine. It uses the OpenIPMI simulator protocol for virtual machines described in :
https://github.com/cminyard/openipmi/blob/master/lanserv/README.vm
and implemented by the 'ipmi-bmc-extern' model on the host side.
To use, start the Aspeed BMC machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,ipv4,server,nowait \ -global driver=aspeed.ibt,property=chardev,value=ipmi0
and the PowerNV machine with :
-chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \ -device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \ -device isa-ipmi-bt,bmc=bmc0,irq=10 -nodefaults
Cc: Hao Wu <wuhaotsh@google.com> Cc: Corey Minyard <cminyard@mvista.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210407171637.777743-20-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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10c47324 |
| 24-Mar-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging
Pull request
Philippe found cases where the 0x%d format string was used, leading to misleading output. The patches lo
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging
Pull request
Philippe found cases where the 0x%d format string was used, leading to misleading output. The patches look harmless and could save people time, so I think it's worth including them in 7.0.
# gpg: Signature made Thu 24 Mar 2022 17:15:20 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: hw: Fix misleading hexadecimal format block: Fix misleading hexadecimal format
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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2539eade |
| 23-Mar-2022 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
hw: Fix misleading hexadecimal format
"0x%u" format is very misleading, replace by "0x%x".
Found running:
$ git grep -E '0x%[0-9]*([lL]*|" ?PRI)[dDuU]' hw/
Inspired-by: Richard Henderson <richa
hw: Fix misleading hexadecimal format
"0x%u" format is very misleading, replace by "0x%x".
Found running:
$ git grep -E '0x%[0-9]*([lL]*|" ?PRI)[dDuU]' hw/
Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20220323114718.58714-3-philippe.mathieu.daude@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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1416688c |
| 10-Mar-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mcayland/tags/q800-updates-for-7.0-20220309' into staging
q800-updates-for-7.0 queue
# gpg: Signature made Wed 09 Mar 2022 10:57:07 GMT # gpg: u
Merge remote-tracking branch 'remotes/mcayland/tags/q800-updates-for-7.0-20220309' into staging
q800-updates-for-7.0 queue
# gpg: Signature made Wed 09 Mar 2022 10:57:07 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* remotes/mcayland/tags/q800-updates-for-7.0-20220309: (22 commits) esp: recreate ESPState current_req after migration esp: include the current PDMA callback in the migration stream esp: convert ESPState pdma_cb from a function pointer to an integer esp: introduce esp_pdma_cb() function esp: introduce esp_set_pdma_cb() function macfb: set initial value of mode control registers in macfb_common_realize() macfb: add VMStateDescription fields for display type and VBL timer macfb: increase number of registers saved in MacfbState macfb: don't use special irq_state and irq_mask variables in MacfbState macfb: add VMStateDescription for MacfbNubusState and MacfbSysBusState macio/pmu.c: remove redundant code mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQs mac_via: make SCSI_DATA (DRQ) bit live rather than latched mos6522: record last_irq_levels in mos6522_set_irq() mos6522: add "info via" HMP command for debugging mos6522: add register names to register read/write trace events mos6522: use device_class_set_parent_reset() to propagate reset to parent mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClass mos6522: switch over to use qdev gpios for IRQs mac_via: use IFR bit flag constants for VIA2 IRQs ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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6c726698 |
| 05-Mar-2022 |
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
mos6522: add register names to register read/write trace events
This helps to follow how the guest is programming the mos6522 when debugging.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@iland
mos6522: add register names to register read/write trace events
This helps to follow how the guest is programming the mos6522 when debugging.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220305150957.5053-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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a8d39f5b |
| 28-Feb-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' into staging
aspeed queue:
* Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rain
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' into staging
aspeed queue:
* Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups
# gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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3671342a |
| 18-Feb-2022 |
Cédric Le Goater <clg@kaod.org> |
aspeed/sdmc: Add trace events
This is useful to analyze changes in the U-Boot RAM driver when SDRAM training is performed.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédri
aspeed/sdmc: Add trace events
This is useful to analyze changes in the U-Boot RAM driver when SDRAM training is performed.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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2c89b5af |
| 20-Jan-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging
target-arm: * hw/intc/arm_gicv3_its: Fix various minor bugs * hw/arm/aspeed: Add the i3c device to the
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-1' into staging
target-arm: * hw/intc/arm_gicv3_its: Fix various minor bugs * hw/arm/aspeed: Add the i3c device to the AST2600 SoC * hw/arm: kudo: add lm75s behind bus 1 switch at 75 * hw/arm/virt: Fix support for running guests on hosts with restricted IPA ranges * hw/intc/arm_gic: Allow reset of the running priority * hw/intc/arm_gic: Implement read of GICC_IIDR * hw/arm/virt: Support for virtio-mem-pci * hw/arm/virt: Support CPU cluster on ARM virt machine * docs/can: convert to restructuredText * hw/net: Move MV88W8618 network device out of hw/arm/ directory * hw/arm/virt: KVM: Enable PAuth when supported by the host
# gpg: Signature made Thu 20 Jan 2022 16:12:12 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20220120-1: (38 commits) hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR hw/intc/arm_gicv3_its: Range-check ICID before indexing into collection table hw/intc/arm_gicv3_its: Check indexes before use, not after hw/intc/arm_gicv3_its: Factor out "find address of table entry" code hw/intc/arm_gicv3_its: Fix return codes in process_mapd() hw/intc/arm_gicv3_its: Fix return codes in process_mapc() hw/intc/arm_gicv3_its: Fix return codes in process_mapti() hw/intc/arm_gicv3_its: Refactor process_its_cmd() to reduce nesting hw/intc/arm_gicv3_its: Fix return codes in process_its_cmd() hw/intc/arm_gicv3_its: Use enum for return value of process_* functions hw/intc/arm_gicv3_its: Don't use data if reading command failed hw/intc/arm_gicv3_its: Fix handling of process_its_cmd() return value hw/intc/arm_gicv3_its: Convert int ID check to num_intids convention hw/intc/arm_gicv3_its: Fix event ID bounds checks hw/arm/aspeed: Add the i3c device to the AST2600 SoC hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model. hw/arm: kudo add lm75s behind bus 1 switch at 75 hw/arm/virt: Drop superfluous checks against highmem hw/arm/virt: Disable highmem devices that don't fit in the PA range hw/arm/virt: Use the PA range to compute the memory map ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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