#
787bbc30 |
| 06-Mar-2018 |
Daniel P. Berrangé <berrange@redhat.com> |
misc, ide: remove use of HWADDR_PRIx in trace events
The trace events all use a uint64_t data type, so should be using the corresponding PRIx64 format, not HWADDR_PRIx which is intended for use with
misc, ide: remove use of HWADDR_PRIx in trace events
The trace events all use a uint64_t data type, so should be using the corresponding PRIx64 format, not HWADDR_PRIx which is intended for use with the 'hwaddr' type.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
show more ...
|
#
f32408f3 |
| 06-Mar-2018 |
Daniel P. Berrangé <berrange@redhat.com> |
misc: don't use hwaddr as a type in trace events
Use types that are defined by QEMU in trace events caused build failures for the UST trace backend:
In file included from trace-ust-all.c:13:0:
misc: don't use hwaddr as a type in trace events
Use types that are defined by QEMU in trace events caused build failures for the UST trace backend:
In file included from trace-ust-all.c:13:0: trace-ust-all.h:11844:206: error: unknown type name ‘hwaddr’
It only knows about C built-in types, and any types that are pulled in from includs of qemu-common.h and lttng/tracepoint.h. This does not include the 'hwaddr' type, so replace it with a uint64_t which is what exec/hwaddr.h defines 'hwaddr' as. This fixes the build failure introduced by
commit 9eb8040c2d2b38e1a40bb6129b1b668fa178fcab Author: Peter Maydell <peter.maydell@linaro.org> Date: Fri Mar 2 10:45:39 2018 +0000
hw/misc/tz-ppc: Model TrustZone peripheral protection controller
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180306134317.836-1-berrange@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
86f4c7e0 |
| 02-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180302' into staging
target-arm queue: * implement FCMA and RDM v8.1 and v8.3 instructions * enable Cortex-M33 v8M core, and p
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180302' into staging
target-arm queue: * implement FCMA and RDM v8.1 and v8.3 instructions * enable Cortex-M33 v8M core, and provide new mps2-an505 board model that uses it * decodetree: Propagate return value from translate subroutines * xlnx-zynqmp: Implement the RTC device
# gpg: Signature made Fri 02 Mar 2018 11:05:40 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180302: (39 commits) target/arm: Enable ARM_FEATURE_V8_FCMA target/arm: Decode t32 simd 3reg and 2reg_scalar extension target/arm: Decode aa32 armv8.3 2-reg-index target/arm: Decode aa32 armv8.3 3-same target/arm: Decode aa64 armv8.3 fcmla target/arm: Decode aa64 armv8.3 fcadd target/arm: Add ARM_FEATURE_V8_FCMA target/arm: Enable ARM_FEATURE_V8_RDM target/arm: Decode aa32 armv8.1 two reg and a scalar target/arm: Decode aa32 armv8.1 three same target/arm: Decode aa64 armv8.1 scalar/vector x indexed element target/arm: Decode aa64 armv8.1 three same extra target/arm: Decode aa64 armv8.1 scalar three same extra target/arm: Refactor disas_simd_indexed size checks target/arm: Refactor disas_simd_indexed decode target/arm: Add ARM_FEATURE_V8_RDM mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image hw/arm/iotkit: Model Arm IOT Kit hw/misc/iotkit-secctl: Add remaining simple registers hw/misc/iotkit-secctl: Add handling for PPCs ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
de343bb6 |
| 02-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton
The Arm IoT Kit includes a "security controller" which is largely a collection of registers for controlling the PPCs and other
hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeleton
The Arm IoT Kit includes a "security controller" which is largely a collection of registers for controlling the PPCs and other bits of glue in the system. This commit provides the initial skeleton of the device, implementing just the ID registers, and a couple of read-only read-as-zero registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-16-peter.maydell@linaro.org
show more ...
|
#
9eb8040c |
| 02-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
hw/misc/tz-ppc: Model TrustZone peripheral protection controller
Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals s
hw/misc/tz-ppc: Model TrustZone peripheral protection controller
Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals so that secure software can configure them to not be accessible to non-secure software.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-15-peter.maydell@linaro.org
show more ...
|
#
9a52d999 |
| 02-Mar-2018 |
Peter Maydell <peter.maydell@linaro.org> |
hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505
The MPS2 AN505 FPGA image includes a "FPGA control block" which is a small set of registers handling LEDs, buttons and some counters.
Signed-o
hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505
The MPS2 AN505 FPGA image includes a "FPGA control block" which is a small set of registers handling LEDs, buttons and some counters.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-14-peter.maydell@linaro.org
show more ...
|
#
7d848450 |
| 12-Feb-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180212' into staging
ppc patch queue 2018-02-12
Here's the accumulatead ppc and pseries related patches for the last while. Highli
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180212' into staging
ppc patch queue 2018-02-12
Here's the accumulatead ppc and pseries related patches for the last while. Highlights are: * A number of Macintosh / CUDA cleanups from Mark Cave-Ayland * An important bug fix (missing "break;") for H_GET_CPU_CHARACTERISTICS * Yet another fix for SMT mode handling * Assorted other cleanups and fixes
# gpg: Signature made Mon 12 Feb 2018 03:39:30 GMT # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.12-20180212: misc: introduce new mos6522 VIA device and enable it for ppc builds cuda: factor out timebase-derived counter value and load time cuda: set timer 1 frequency property to CUDA_TIMER_FREQ cuda: don't call cuda_update() when writing to ACR register cuda: minor cosmetic tidy-ups to get_next_irq_time() cuda: rename frequency property to tb_frequency cuda: introduce CUDAState parameter to get_counter() spapr: set vsmt to MAX(8, smp_threads) cuda: don't allow writes to port output pins cuda: do not use old_mmio accesses hw/ppc: rename functions in comments spapr: add missing break in h_get_cpu_characteristics()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
51f233ec |
| 09-Feb-2018 |
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
misc: introduce new mos6522 VIA device and enable it for ppc builds
The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard
misc: introduce new mos6522 VIA device and enable it for ppc builds
The MOS6522 VIA forms the bridge part of several Mac devices, including the Mac via-cuda and via-pmu devices. Introduce a standard mos6522 device that can be shared amongst multiple implementations.
This is effectively taking the 6522 parts out of cuda.c and turning them into a separate device whilst also applying some style tidy-ups and including a conversion to trace-events.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
show more ...
|
#
f31cd9e4 |
| 09-Feb-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180209' into staging
target-arm queue: * Support M profile derived exceptions on exception entry and exit * Implement AArch64
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180209' into staging
target-arm queue: * Support M profile derived exceptions on exception entry and exit * Implement AArch64 v8.2 crypto insns (SHA-512, SHA-3, SM3, SM4) * Implement working i.MX6 SD controller * Various devices preparatory to i.MX7 support * Preparatory patches for SVE emulation * v8M: Fix bug in implementation of 'TT' insn * Give useful error if user tries to use userspace GICv3 with KVM
# gpg: Signature made Fri 09 Feb 2018 11:01:23 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180209: (30 commits) hw/core/generic-loader: Allow PC to be set on command line target/arm/translate.c: Fix missing 'break' for TT insns target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM target/arm: Add SVE state to TB->FLAGS target/arm: Add ZCR_ELx target/arm: Add SVE to migration state target/arm: Add predicate registers for SVE target/arm: Expand vector registers for SVE hw/arm: Move virt's PSCI DT fixup code to arm/boot.c usb: Add basic code to emulate Chipidea USB IP i.MX: Add implementation of i.MX7 GPR IP block i.MX: Add i.MX7 GPT variant i.MX: Add code to emulate GPCv2 IP block i.MX: Add code to emulate i.MX7 SNVS IP-block i.MX: Add code to emulate i.MX2 watchdog IP block i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHC sdhci: Add i.MX specific subtype of SDHCI target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support target/arm: implement SM4 instructions ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
30b2f870 |
| 09-Feb-2018 |
Andrey Smirnov <andrew.smirnov@gmail.com> |
i.MX: Add implementation of i.MX7 GPR IP block
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: P
i.MX: Add implementation of i.MX7 GPR IP block
Add minimal code needed to allow upstream Linux guest to boot.
Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: ppc-for-2.11-20171127, ppc-for-2.11-20171122, v2.11.0-rc2, ppc-for-2.11-20171120, v2.11.0-rc1, ppc-for-2.11-20171114, ppc-for-2.11-20171108, v2.11.0-rc0, ppc-for-2.11-20171017, v2.10.1, ppc-for-2.11-20170927 |
|
#
0a8066f0 |
| 21-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170921' into staging
target-arm queue: * more preparatory work for v8M support * convert some omap devices away from old_mmio
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170921' into staging
target-arm queue: * more preparatory work for v8M support * convert some omap devices away from old_mmio * remove out of date ARM ARM section references in comments * add the Smartfusion2 board
# gpg: Signature made Thu 21 Sep 2017 17:40:40 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170921: (31 commits) msf2: Add Emcraft's Smartfusion2 SOM kit msf2: Add Smartfusion2 SoC msf2: Add Smartfusion2 SPI controller msf2: Microsemi Smartfusion2 System Register block msf2: Add Smartfusion2 System timer hw/arm/omap2.c: Don't use old_mmio hw/i2c/omap_i2c.c: Don't use old_mmio hw/timer/omap_gptimer: Don't use old_mmio hw/timer/omap_synctimer.c: Don't use old_mmio hw/gpio/omap_gpio.c: Don't use old_mmio hw/arm/palm.c: Don't use old_mmio for static_ops target/arm: Remove out of date ARM ARM section references in A64 decoder nvic: Support banked exceptions in acknowledge and complete nvic: Make SHCSR banked for v8M nvic: Make ICSR banked for v8M target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index() nvic: Handle v8M changes in nvic_exec_prio() nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear nvic: Implement v8M changes to fixed priority exceptions nvic: In escalation to HardFault, support HF not being priority -1 ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
0ee1e1f4 |
| 20-Sep-2017 |
Subbaraya Sundeep <sundeep.lkml@gmail.com> |
msf2: Microsemi Smartfusion2 System Register block
Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest.
Signed-off-by: Subbaraya Sundeep <sundeep.lk
msf2: Microsemi Smartfusion2 System Register block
Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: ppc-for-2.11-20170915, ppc-for-2.11-20170908, v2.9.1, v2.10.0, v2.10.0-rc4, ppc-for-2.10-20170823, ppc-for-2.10-20170822, v2.10.0-rc3, ppc-for-2.10-20170809, v2.10.0-rc2, v2.10.0-rc1 |
|
#
7d48cf81 |
| 01-Aug-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Pull request
Fixes for inconsistencies in the trace event format strings, broken trace_event_get_state() usage
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Pull request
Fixes for inconsistencies in the trace event format strings, broken trace_event_get_state() usage, and handle_qmp_command() fix.
# gpg: Signature made Tue 01 Aug 2017 14:16:05 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/tracing-pull-request: monitor: Reduce handle_qmp_command() tracing overhead trace-events: fix code style: print 0x before hex numbers checkpatch: check trace-events code style trace-events: fix code style: %# -> 0x% coding_style: add point about 0x in trace-events trace: add trace_event_get_state_backends() trace: add TRACE_<event>_BACKEND_DSTATE() trace: ensure unique function / variable names per .stp file trace: ensure .stp files are rebuilt if trace tool source changes
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
8908eb1a |
| 31-Jul-2017 |
Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> |
trace-events: fix code style: print 0x before hex numbers
The only exception are groups of numers separated by symbols '.', ' ', ':', '/', like 'ab.09.7d'.
This patch is made by the following:
> f
trace-events: fix code style: print 0x before hex numbers
The only exception are groups of numers separated by symbols '.', ' ', ':', '/', like 'ab.09.7d'.
This patch is made by the following:
> find . -name trace-events | xargs python script.py
where script.py is the following python script: ========================= #!/usr/bin/env python
import sys import re import fileinput
rhex = '%[-+ *.0-9]*(?:[hljztL]|ll|hh)?(?:x|X|"\s*PRI[xX][^"]*"?)' rgroup = re.compile('((?:' + rhex + '[.:/ ])+' + rhex + ')') rbad = re.compile('(?<!0x)' + rhex)
files = sys.argv[1:]
for fname in files: for line in fileinput.input(fname, inplace=True): arr = re.split(rgroup, line) for i in range(0, len(arr), 2): arr[i] = re.sub(rbad, '0x\g<0>', arr[i])
sys.stdout.write(''.join(arr)) =========================
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20170731160135.12101-5-vsementsov@virtuozzo.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
#
25dd0e77 |
| 31-Jul-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging
trivial patches for 2017-07-31
# gpg: Signature made Mon 31 Jul 2017 11:18:57 BST # gpg: using RSA
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into staging
trivial patches for 2017-07-31
# gpg: Signature made Mon 31 Jul 2017 11:18:57 BST # gpg: using RSA key 0x701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59
* remotes/mjt/tags/trivial-patches-fetch: (25 commits) docs: fix broken paths to docs/specs/ivshmem-spec.txt docs: fix broken paths to docs/config/ich9-ehci-uhci.cfg docs: fix broken paths to docs/devel/tracing.txt docs: fix broken paths to docs/devel/atomics.txt docs: fix broken paths to docs/devel/qapi-code-gen.txt docs: fix broken paths to docs/interop/qcow2.txt docs: fix broken paths to docs/interop dir thunk: assert nb_fields is valid syscall: check inotify() and eventfd() return value syscall: fix use of uninitialized values syscall: fix dereference of undefined pointer linux-user/sh4: fix incorrect memory write m68k/translate: fix incorrect copy/paste net/eth: fix incorrect check of iov_to_buf() return value ui/vnc: fix leak of SocketAddress ** qcow2: fix null pointer dereference ivshmem: fix incorrect error handling in ivshmem_recv_msg() loader: check get_image_size() return value tests: add missing dependency to build QTEST_QEMU_BINARY qemu-system-tricore: segfault when entering "x 0" on the monitor ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: ppc-for-2.10-20170731 |
|
#
87e0331c |
| 28-Jul-2017 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
docs: fix broken paths to docs/devel/tracing.txt
With the move of some docs/ to docs/devel/ on ac06724a71, no references were updated.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Review
docs: fix broken paths to docs/devel/tracing.txt
With the move of some docs/ to docs/devel/ on ac06724a71, no references were updated.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
show more ...
|
Revision tags: v2.10.0-rc0, ppc-for-2.10-20170725 |
|
#
6c459156 |
| 18-Jul-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170717' into staging
target-arm queue: * new model of the ARM MPS2/MPS2+ FPGA based development board * clean up DISAS_* exit
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170717' into staging
target-arm queue: * new model of the ARM MPS2/MPS2+ FPGA based development board * clean up DISAS_* exit conditions and fix various regressions since commits e75449a346 8a6b28c7b5 (in particular including ones which broke OP-TEE guests) * make Cortex-M3 and M4 correctly default to 8 PMSA regions
# gpg: Signature made Mon 17 Jul 2017 13:43:45 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170717: MAINTAINERS: Add entries for MPS2 board hw/arm/mps2: Add ethernet hw/arm/mps2: Add SCC hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller hw/arm/mps2: Add timers hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device hw/arm/mps2: Add UARTs hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models target/arm: use DISAS_EXIT for eret handling target/arm: use gen_goto_tb for ISB handling target/arm/translate: ensure gen_goto_tb sets exit flags target/arm/translate.h: expand comment on DISAS_EXIT target/arm/translate: make DISAS_UPDATE match declared semantics include/exec/exec-all: document common exit conditions target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions qdev: support properties which don't set a default value qdev-properties.h: Explicitly set the default value for arraylen properties
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
dd73185b |
| 17-Jul-2017 |
Peter Maydell <peter.maydell@linaro.org> |
hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller
Implement a model of the Serial Communication Controller (SCC) found in MPS2 FPGA images.
The primary purpose of this device is to c
hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller
Implement a model of the Serial Communication Controller (SCC) found in MPS2 FPGA images.
The primary purpose of this device is to communicate with the Motherboard Configuration Controller (MCC) which is located on the MPS board itself, outside the FPGA image. This is used for programming the MPS clock generators. The SCC also has some basic ID registers and an output for the board LEDs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-7-git-send-email-peter.maydell@linaro.org
show more ...
|
Revision tags: ppc-for-2.10-20170717, ppc-for-2.10-20170714, ppc-for-2.10-20170711, ppc-for-2.10-20170630, ppc-for-2.10-20170609, ppc-for-2.10-20170606, ppc-for-2.10-20170525, ppc-for-2.10-20170511, ppc-for-2.10-20170510, ppc-for-2.10-20170426, ppc-for-2.10-20170424, v2.8.1.1, v2.9.0, v2.9.0-rc5, v2.9.0-rc4, v2.9.0-rc3, ppc-for-2.9-20170403, v2.8.1, ppc-for-2.9-20170329, v2.9.0-rc2, ppc-for-2.9-20170323, v2.9.0-rc1, v2.9.0-rc0, ppc-for-2.9-20170314, ppc-for-2.9-20170306, submodule-update-20170303, ppc-for-2.9-20170303, ppc-for-2.9-20170301, ppc-for-2.9-20170222, isa-cleanup-20170206, ppc-for-2.9-20170202, ppc-for-2.9-20170112, master-20170112, v2.7.1, v2.8.0, v2.8.0-rc4, v2.8.0-rc3, ppc-for-2.8-20161201, v2.8.0-rc2, ppc-for-2.8-20161123, v2.8.0-rc1, isa-cleanup-20161118, qemu-kvm-1.5.3-127.el7, v2.8.0-rc0, ppc-for-2.8-20161115, qemu-kvm-1.5.3-126.el7_3.1, qemu-kvm-0.12.1.2-2.496.el6, ppc-for-2.8-20161028, qemu-kvm-0.12.1.2-2.495.el6, ppc-for-2.8-20161026, ppc-for-2.8-20161017, qemu-kvm-rhev-2.3.0-31.el7_2.23, ppc-for-2.7-20161013, qemu-kvm-1.5.3-105.el7_2.10, ppc-for-2.8-20161006, qemu-kvm-1.5.3-105.el7_2.9, v2.6.2, RHELSA-7.3_qemu-kvm-rhev, qemu-kvm-rhev-2.6.0-28.el7, RHEL-7.3_qemu-kvm-rhev, qemu-kvm-rhev-2.6.0-27.el7, ppc-for-2.8-20160923, qemu-kvm-0.12.1.2-2.494.el6, ppc-for-2.8-20160922, RHEL-7.3_qemu-kvm, qemu-kvm-1.5.3-126.el7, qemu-kvm-rhev-2.6.0-26.el7, vfio-fixes-20160915.0, qemu-kvm-1.5.3-125.el7, qemu-kvm-rhev-2.3.0-31.el7_2.22, qemu-kvm-rhev-2.6.0-25.el7, qemu-kvm-1.5.3-124.el7, qemu-kvm-rhev-2.6.0-24.el7, qemu-kvm-1.5.3-123.el7, qemu-kvm-0.12.1.2-2.415.el6_5.16, ppc-for-2.8-20160907, qemu-kvm-rhev-2.6.0-23.el7, ppc-for-2.8-20160906, v2.7.0, RHEL-7.3-qemu-guest-agent, qemu-guest-agent-2.5.0-3.el7, v2.7.0-rc5, qemu-kvm-1.5.3-122.el7, qemu-kvm-rhev-2.6.0-22.el7, v2.7.0-rc4, v2.6.1, v2.7.0-rc3, qemu-kvm-rhev-2.6.0-21.el7, qemu-kvm-1.5.3-105.el7_2.8, ppc-for-2.7-20160815, qemu-kvm-rhev-2.6.0-20.el7, ppc-for-2.7-20160810, v2.7.0-rc2, ppc-for-2.7-20160808, qemu-kvm-rhev-2.6.0-19.el7, ppc-for-2.7-20160803, qemu-kvm-rhev-2.6.0-18.el7, qemu-kvm-1.5.3-105.el7_2.7, qemu-kvm-rhev-2.3.0-31.el7_2.21, qemu-kvm-1.5.3-121.el7, v2.7.0-rc1, qemu-kvm-rhev-2.6.0-17.el7, qemu-kvm-1.5.3-120.el7, ppc-for-2.7-20160729, qemu-kvm-0.12.1.2-2.493.el6, qemu-kvm-1.5.3-105.el7_2.6, qemu-kvm-0.12.1.2-2.491.el6_8.3, qemu-kvm-rhev-2.3.0-31.el7_2.20, qemu-kvm-1.5.3-119.el7, qemu-kvm-rhev-2.6.0-16.el7, ppc-for-2.7-20160726, v2.7.0-rc0, qemu-kvm-rhev-2.6.0-15.el7, qemu-kvm-rhev-2.3.0-31.el7_2.19, qemu-kvm-rhev-2.6.0-14.el7, qemu-kvm-1.5.3-118.el7, vfio-update-20160718.0, ppc-for-2.7-20160718, qemu-kvm-1.5.3-117.el7, qemu-kvm-rhev-2.6.0-13.el7, qemu-kvm-rhev-2.6.0-12.el7, qemu-kvm-rhev-2.3.0-31.el7_2.18, ppc-for-2.7-20160705, qemu-kvm-rhev-2.6.0-11.el7, qemu-kvm-1.5.3-105.el7_2.5, ppc-for-2.7-20160701, vfio-update-20160630.0, qemu-kvm-0.12.1.2-2.492.el6, qemu-kvm-rhev-2.6.0-10.el7, qemu-kvm-rhev-2.3.0-31.el7_2.17, qemu-kvm-1.5.3-116.el7 |
|
#
98c710f2 |
| 27-Jun-2016 |
Andrew Jeffery <andrew@aj.id.au> |
Merge remote-tracking branch 'clg/aspeed'
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
|
#
b5ab61c0 |
| 27-Jun-2016 |
Andrew Jeffery <andrew@aj.id.au> |
hw/misc: Add a model for the ASPEED System Control Unit
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control
hw/misc: Add a model for the ASPEED System Control Unit
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes.
Firmware makes heavy use of the state to determine how to boot, but the reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev property is exposed so that the integrating SoC model can configure the silicon revision, which in-turn selects the appropriate reset values. Further qdev properties are exposed so the board model can configure the board-dependent hardware strapping.
Almost all provided AST2400 reset values are specified by the datasheet. The notable exception is SOC_SCRATCH1, where we mark the DRAM as successfully initialised to avoid unnecessary dark corners in the SoC's u-boot support.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
aba5d976 |
| 15-Aug-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
# gpg: Signature made Fri 12 Aug 2016 11:48:03 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
# gpg: Signature made Fri 12 Aug 2016 11:48:03 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/tracing-pull-request: trace-events: fix first line comment in trace-events
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
e723b871 |
| 08-Aug-2016 |
Laurent Vivier <lvivier@redhat.com> |
trace-events: fix first line comment in trace-events
Documentation is docs/tracing.txt instead of docs/trace-events.txt.
find . -name trace-events -exec \ sed -i "s?See docs/trace-events.txt f
trace-events: fix first line comment in trace-events
Documentation is docs/tracing.txt instead of docs/trace-events.txt.
find . -name trace-events -exec \ sed -i "s?See docs/trace-events.txt for syntax documentation.?See docs/tracing.txt for syntax documentation.?" \ {} \;
Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-id: 1470669081-17860-1-git-send-email-lvivier@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
#
f12103af |
| 27-Jun-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160627' into staging
target-arm queue: * arm_gicv3: add missing 'break' statements * cadence_uart: protect against transmit er
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160627' into staging
target-arm queue: * arm_gicv3: add missing 'break' statements * cadence_uart: protect against transmit errors * cadence_gem: avoid infinite loops with misconfigured buffer * cadence_gem: set the 'last' bit when 'wrap' is set * reenable tmp105 test case * palmetto-bmc: add ASPEED system control unit model * m25p80: add new 512Mbit and 1Gbit devices
# gpg: Signature made Mon 27 Jun 2016 15:43:42 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20160627: m25p80: Fix WINBOND fast read command handling m25p80: New flash devices. m25p80: Fast read commands family changes. m25p80: Introduce configuration registers. m25p80: Introduce quad and equad modes. m25p80: Add additional flash commands: m25p80: Introduce COLLECTING_VAR_LEN_DATA state. m25p80: Allow more than four banks. m25p80: Make a table for JEDEC ID. m25p80: Replace JEDEC ID masking with function. palmetto-bmc: Configure the SCU's hardware strapping register ast2400: Integrate the SCU model and set silicon revision hw/misc: Add a model for the ASPEED System Control Unit arm: Re-enable tmp105 test cadence_gem: Set the last bit when wrap is set cadence_gem: Avoid infinite loops with a misconfigured buffer cadence_uart: Protect against transmit errors hw/intc/arm_gicv3: Add missing break
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
1c8a2388 |
| 27-Jun-2016 |
Andrew Jeffery <andrew@aj.id.au> |
hw/misc: Add a model for the ASPEED System Control Unit
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control
hw/misc: Add a model for the ASPEED System Control Unit
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes.
Firmware makes heavy use of the state to determine how to boot, but the reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev property is exposed so that the integrating SoC model can configure the silicon revision, which in-turn selects the appropriate reset values. Further qdev properties are exposed so the board model can configure the board-dependent hardware strapping.
Almost all provided AST2400 reset values are specified by the datasheet. The notable exception is SOC_SCRATCH1, where we mark the DRAM as successfully initialised to avoid unnecessary dark corners in the SoC's u-boot support.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1466744305-23163-2-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: drop unnecessary inttypes.h include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: ppc-for-2.7-20160627, qemu-kvm-rhev-2.6.0-9.el7, ppc-for-2.7-20160623, qemu-kvm-0.12.1.2-2.491.el6_8.2, qemu-kvm-rhev-2.6.0-8.el7 |
|
#
b0ad00b8 |
| 20-Jun-2016 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
# gpg: Signature made Mon 20 Jun 2016 21:29:27 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
# gpg: Signature made Mon 20 Jun 2016 21:29:27 BST # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/tracing-pull-request: (42 commits) trace: split out trace events for linux-user/ directory trace: split out trace events for qom/ directory trace: split out trace events for target-ppc/ directory trace: split out trace events for target-s390x/ directory trace: split out trace events for target-sparc/ directory trace: split out trace events for net/ directory trace: split out trace events for audio/ directory trace: split out trace events for ui/ directory trace: split out trace events for hw/alpha/ directory trace: split out trace events for hw/arm/ directory trace: split out trace events for hw/acpi/ directory trace: split out trace events for hw/vfio/ directory trace: split out trace events for hw/s390x/ directory trace: split out trace events for hw/pci/ directory trace: split out trace events for hw/ppc/ directory trace: split out trace events for hw/9pfs/ directory trace: split out trace events for hw/i386/ directory trace: split out trace events for hw/isa/ directory trace: split out trace events for hw/sd/ directory trace: split out trace events for hw/sparc/ directory ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|