| e6b0408a | 04-Jan-2022 |
Jim Shu <jim.shu@sifive.com> |
hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit acc
hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20220104063408.658169-3-jim.shu@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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| 47b5fbf5 | 27-Sep-2021 |
Bin Meng <bmeng.cn@gmail.com> |
hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
If Control.run bit is set while not preserving the Control.claim
bit, the DMA transfer shall not be started.
The following result is PD
hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
If Control.run bit is set while not preserving the Control.claim
bit, the DMA transfer shall not be started.
The following result is PDMA tested in U-Boot on Unleashed board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
=> mw.l 0x3000000 0x1 <= Claim channel 0
=> mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x2 <= NextBytes = 2
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000001 55000000 00000002 00000000 .......U........
03000010: 84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x2 <= Set channel 0 run bit only
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000000 55000000 00000002 00000000 .......U........
03000010: 84000000 00000000 84001000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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| ae000c5f | 12-Sep-2021 |
Frank Chang <frank.chang@sifive.com> |
hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
Real PDMA doesn't set Control.error if there are 0 bytes to be
transferred. The DMA transfer is still success.
The following resu
hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
Real PDMA doesn't set Control.error if there are 0 bytes to be
transferred. The DMA transfer is still success.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
=> mw.l 0x3000000 0x1 <= Claim channel 0
=> mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x0 <= NextBytes = 0
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000001 55000000 00000000 00000000 .......U........
03000010: 84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 40000001 55000000 00000000 00000000 ...@...U........
03000010: 84000000 00000000 84001000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210912130553.179501-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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| e22d90f5 | 12-Sep-2021 |
Green Wan <green.wan@sifive.com> |
hw/dma: sifive_pdma: allow non-multiple transaction size transactions
Real PDMA is able to deal with non-multiple transaction size transactions.
The following result is PDMA tested in U-Boot on Unm
hw/dma: sifive_pdma: allow non-multiple transaction size transactions
Real PDMA is able to deal with non-multiple transaction size transactions.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
=> mw.l 0x3000000 0x1 <= Claim channel 0
=> mw.l 0x3000004 0x11000000 <= wsize = rsize = 1 (2^1 = 2 bytes)
=> mw.q 0x3000008 0x3 <= NextBytes = 3
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000001 11000000 00000003 00000000 ................
03000010: 84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 40000001 11000000 00000003 00000000 ...@............
03000010: 84000000 00000000 84001000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87345678 xV4.
84001000: 12345678 xV4.
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210912130553.179501-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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| 9a8c26c0 | 12-Sep-2021 |
Frank Chang <frank.chang@sifive.com> |
hw/dma: sifive_pdma: claim bit must be set before DMA transactions
Real PDMA must have Control.claim bit to be set before
Control.run bit is set to start any DMA transactions.
Otherwise nothing will
hw/dma: sifive_pdma: claim bit must be set before DMA transactions
Real PDMA must have Control.claim bit to be set before
Control.run bit is set to start any DMA transactions.
Otherwise nothing will be transferred.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
(Channel 0 is not claimed)
=> mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x2 <= NextBytes = 2
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000000 55000000 00000002 00000000 .......U........
03000010: 84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000001 66000000 00000000 00000000 .......f........
03000010: 00000000 00000000 00000000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210912130553.179501-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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| 783dbab1 | 19-Aug-2021 |
Philippe Mathieu-Daudé <philmd@redhat.com> |
hw/dma/xlnx-zdma Always expect 'dma' link property to be set
Simplify by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
remov
hw/dma/xlnx-zdma Always expect 'dma' link property to be set
Simplify by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
removing need for heap allocation.
Update the Xilinx ZynqMP / Versal SoC models to pass the default
system memory instead of a NULL value.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210819163422.2863447-5-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| c31b7f59 | 19-Aug-2021 |
Philippe Mathieu-Daudé <philmd@redhat.com> |
hw/dma/xlnx_csu_dma: Always expect 'dma' link property to be set
Simplify by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
r
hw/dma/xlnx_csu_dma: Always expect 'dma' link property to be set
Simplify by always passing a MemoryRegion property to the device.
Doing so we can move the AddressSpace field to the device struct,
removing need for heap allocation.
Update the Xilinx ZynqMP SoC model to pass the default system
memory instead of a NULL value.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210819163422.2863447-4-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
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