ASoC: Intel: Skylake: add DSP platform widget event handlers

The Skylake driver topology model tries to model the firmware
rule for pipeline and module creation.
The creation rule is

ASoC: Intel: Skylake: add DSP platform widget event handlers

The Skylake driver topology model tries to model the firmware
rule for pipeline and module creation.
The creation rule is:
- Create Pipe
- Add modules to Pipe
- Connect the modules (bind)
- Start the pipes

Similarly destroy rule is:
- Stop the pipe
- Disconnect it (unbind)
- Delete the pipe

In driver we use Mixer, as there will always be ONE mixer in a
pipeline to model a pipe. The modules in pipe are modelled as PGA
widgets. The DAPM sequencing rules (mixer and then PGA) are used
to create the sequence DSP expects as depicted above, and then
widget handlers for PMU and PMD events help in that.

This patch adds widget event handlers for PRE/POST PMU and
PRE/POST PMD event for mixer and pga modules. These event
handlers invoke pipeline creation, destroy, module creation,
module bind, unbind and pipeline bind unbind

Event handler sequencing is implement to target the DSP FW
sequence expectations to enable path from source to sink pipe for
Playback/Capture.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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ASoC: Intel: Skylake: Add pipe and modules handlers

SKL driver needs to instantiate pipelines and modules in the DSP.
The topology in the DSP is modelled as DAPM graph with a PGA
rep

ASoC: Intel: Skylake: Add pipe and modules handlers

SKL driver needs to instantiate pipelines and modules in the DSP.
The topology in the DSP is modelled as DAPM graph with a PGA
representing a module instance and mixer representing a pipeline
for a group of modules along with the mixer itself.

Here we start adding building block for handling these. We add
resource checks (memory/compute) for pipelines, find the modules
in a pipeline, init modules in a pipe and lastly bind/unbind
modules in a pipe These will be used by pipe event handlers in
subsequent patches

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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ASoC: Intel: Skylake: Add pipe management helpers

To manage DSP we need to create processing pipeline and on cleanup destroy
them. So we add create and destroy routines for pipelines The

ASoC: Intel: Skylake: Add pipe management helpers

To manage DSP we need to create processing pipeline and on cleanup destroy
them. So we add create and destroy routines for pipelines The pipelines need
to to be executed so we add pipeline run and stop routines
All these send required IPCs to DSP using IPC routines added earlier

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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ASoC: Intel: Skylake: Add DSP module init and binding routines

A module needs to be instantiated and then connected with other modules. On
cleanup we need to disconnect the module.
T

ASoC: Intel: Skylake: Add DSP module init and binding routines

A module needs to be instantiated and then connected with other modules. On
cleanup we need to disconnect the module.
This is achieved by helpers module init, bind and unbind which are added
here

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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ASoC: Intel: Skylake: Add helpers for SRC and converter modules

SRC and converter modules are required to do frequency and channel
conversion in DSP. Both take base module configuration

ASoC: Intel: Skylake: Add helpers for SRC and converter modules

SRC and converter modules are required to do frequency and channel
conversion in DSP. Both take base module configuration and additional SRC
and converter parameters. The helpers here are added to calculate the values
for these modules

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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ASoC: Intel: Skylake: Add helpers for DSP module configuration

This adds helper functions to calculate parameters required for base module
format and copier module. A generic module is m

ASoC: Intel: Skylake: Add helpers for DSP module configuration

This adds helper functions to calculate parameters required for base module
format and copier module. A generic module is modelled by base module.
Copier module is responsible for getting/sending data to FE (host DMAs) and
BE (link HDA DMA, SSP, PDM)
This also ads module pin management helpers which help in finding pins to
use or freeing them up

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

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