ASoC: Intel: Skylake: Fix support for multiple pins in a module

For supporting multiple dynamic pins, module state check is
incorrect. In case of unbind, module state need to be changed

ASoC: Intel: Skylake: Fix support for multiple pins in a module

For supporting multiple dynamic pins, module state check is
incorrect. In case of unbind, module state need to be changed to
uninit if all pins in the module is is unbind state.
To handle module state correctly add pin state and use pin
state check to set module state correctly.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Fix to ignore blob check if link type is HDA

If link type is HDA, NHLT blob is null, as NHLT defines non HDA
links only. So we should ignore blob query for HDA lin

ASoC: Intel: Skylake: Fix to ignore blob check if link type is HDA

If link type is HDA, NHLT blob is null, as NHLT defines non HDA
links only. So we should ignore blob query for HDA links.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Fix to add 32 bit in update FE params

In case of 32 bit, the FE update params returns error as it falls
thru to default case. This patch adds 32 bit depth handling

ASoC: Intel: Skylake: Fix to add 32 bit in update FE params

In case of 32 bit, the FE update params returns error as it falls
thru to default case. This patch adds 32 bit depth handling in
update FE params.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Fix to correct check for non DSP widget

To get the FE copier module, the check to ignore non DSP widgets
was wrong. This path corrects the check to ignore non DSP w

ASoC: Intel: Skylake: Fix to correct check for non DSP widget

To get the FE copier module, the check to ignore non DSP widgets
was wrong. This path corrects the check to ignore non DSP widget.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Add support to topology for module static pin

Some module pin connection are static and defined by the topology.
This patch adds support for static pin definitions

ASoC: Intel: Skylake: Add support to topology for module static pin

Some module pin connection are static and defined by the topology.
This patch adds support for static pin definitions in topology widget
private data

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Fix to fill all sink/source pipe params

Currently params only for first copier widget identified in the
source/sink path is queried from NHLT. In the dapm route the

ASoC: Intel: Skylake: Fix to fill all sink/source pipe params

Currently params only for first copier widget identified in the
source/sink path is queried from NHLT. In the dapm route the
playback/capture widget may be connected to more than one copier
widget. This patch adds return check to return only for any error
case.

Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Fix to use correct macros for the path iteration

In case of playback, for the BE dai source path should be iterated to find
the pipe params. With sink path iterated

ASoC: Intel: Skylake: Fix to use correct macros for the path iteration

In case of playback, for the BE dai source path should be iterated to find
the pipe params. With sink path iterated, this resulted in a loop and kernel
panic with page request failure.
Similar are the cases for Capture and FE dais. Using correct macros to fix
the panic

Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Remove BE copier blob memcpy

The BE copier private data allowed endpoint configuration blobs, now these
are queried from BIOS, we don't need to copy the blob, but o

ASoC: Intel: Skylake: Remove BE copier blob memcpy

The BE copier private data allowed endpoint configuration blobs, now these
are queried from BIOS, we don't need to copy the blob, but only capability.

Removing the blob from private data will not allocate memory for module
specific config in which case memcpy will fail. Fix is to assign the ptr
queried from the NHLT table for the endpoint configuration.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Modify the log level

dev_info is too noisy for tplg wiget loading, so move it to
debug level

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-of

ASoC: Intel: Skylake: Modify the log level

dev_info is too noisy for tplg wiget loading, so move it to
debug level

Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Initialize and load DSP controls

Initialize and creates DSP controls if processing pipe capability
is supported by HW. Updates the dma_id, hw_params to module param

ASoC: Intel: Skylake: Initialize and load DSP controls

Initialize and creates DSP controls if processing pipe capability
is supported by HW. Updates the dma_id, hw_params to module param
to be used when DSP module has to be configured.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Add topology core init and handlers

The SKL driver does not code DSP topology in driver. It uses the
newly added ASoC topology core to parse the topology informatio

ASoC: Intel: Skylake: Add topology core init and handlers

The SKL driver does not code DSP topology in driver. It uses the
newly added ASoC topology core to parse the topology information
(controls, widgets and map) from topology binary.
Each topology element passed private data which contains
information that driver used to identify the module instance
within firmware and send IPCs for that module to DSP firmware
along with parameters.
This patch adds init routine to invoke topology load and callback
for topology creation.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Add FE and BE hw_params handling

For FE and BE, the PCM parameters come from FE and BE hw_params
values passed. For a FE we convert the FE params to DSP expected

ASoC: Intel: Skylake: Add FE and BE hw_params handling

For FE and BE, the PCM parameters come from FE and BE hw_params
values passed. For a FE we convert the FE params to DSP expected
module format and pass to DSP. For a BE we need to find the
gateway settings (i2s/PDM) to be applied. These are queried from
NHLT table and applied.

Further for BE based on direction the settings are applied as
either source or destination parameters.

These helpers here allow the format to be calculated and queried
as per firmware format.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: add DSP platform widget event handlers

The Skylake driver topology model tries to model the firmware
rule for pipeline and module creation.
The creation rule is

ASoC: Intel: Skylake: add DSP platform widget event handlers

The Skylake driver topology model tries to model the firmware
rule for pipeline and module creation.
The creation rule is:
- Create Pipe
- Add modules to Pipe
- Connect the modules (bind)
- Start the pipes

Similarly destroy rule is:
- Stop the pipe
- Disconnect it (unbind)
- Delete the pipe

In driver we use Mixer, as there will always be ONE mixer in a
pipeline to model a pipe. The modules in pipe are modelled as PGA
widgets. The DAPM sequencing rules (mixer and then PGA) are used
to create the sequence DSP expects as depicted above, and then
widget handlers for PMU and PMD events help in that.

This patch adds widget event handlers for PRE/POST PMU and
PRE/POST PMD event for mixer and pga modules. These event
handlers invoke pipeline creation, destroy, module creation,
module bind, unbind and pipeline bind unbind

Event handler sequencing is implement to target the DSP FW
sequence expectations to enable path from source to sink pipe for
Playback/Capture.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Add module configuration helpers

To configure a module, driver needs to send input and output PCM
params for a module in DSP. The FE PCM params come from hw_params

ASoC: Intel: Skylake: Add module configuration helpers

To configure a module, driver needs to send input and output PCM
params for a module in DSP. The FE PCM params come from hw_params
ie from user, for a BE they also come from hw_params but from
BE-link fixups.
So based on PCM params required driver has to find a converter
module (src/updown/format) and then do the conversion and
calculate PCM params in these pipelines In this patch we add the
helper modules which allow driver to do these calculations.

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...

ASoC: Intel: Skylake: Add pipe and modules handlers

SKL driver needs to instantiate pipelines and modules in the DSP.
The topology in the DSP is modelled as DAPM graph with a PGA
rep

ASoC: Intel: Skylake: Add pipe and modules handlers

SKL driver needs to instantiate pipelines and modules in the DSP.
The topology in the DSP is modelled as DAPM graph with a PGA
representing a module instance and mixer representing a pipeline
for a group of modules along with the mixer itself.

Here we start adding building block for handling these. We add
resource checks (memory/compute) for pipelines, find the modules
in a pipeline, init modules in a pipe and lastly bind/unbind
modules in a pipe These will be used by pipe event handlers in
subsequent patches

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

show more ...