| #
b6633d77 |
| 20-Nov-2020 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM
The J7200 SOM have additional io expander which is used to control several
SOM level muxes to make sure that the correct sign
arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM
The J7200 SOM have additional io expander which is used to control several
SOM level muxes to make sure that the correct signals are routed to the
correct pin on the SOM <-> CPB connectors.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20201120073533.24486-2-peter.ujfalusi@ti.com
show more ...
|
| #
4cc34aa8 |
| 13-Nov-2020 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: am65/j721e/j7200: Mark firmware used uart as "reserved"
Follow the device tree standards that states to set the
status="reserved" if an device is operational, but used by a non-linux
arm64: dts: ti: am65/j721e/j7200: Mark firmware used uart as "reserved"
Follow the device tree standards that states to set the
status="reserved" if an device is operational, but used by a non-linux
firmware in the system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20201113211826.13087-6-nm@ti.com
show more ...
|
|
Revision tags: v5.8.17 |
|
| #
e6b45168 |
| 29-Oct-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support
J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node
for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Si
arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support
J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node
for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20201029050950.4500-1-vigneshr@ti.com
show more ...
|
| #
c8815d6f |
| 26-May-2021 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am654x/j721e/j7200-common-proc-board: Fix MCU_RGMII1_TXC direction
[ Upstream commit 69db725cdb2b803af67897a08ea54467d11f6020 ]
The MCU RGMII MCU_RGMII1_TXC pin is defined as inp
arm64: dts: ti: k3-am654x/j721e/j7200-common-proc-board: Fix MCU_RGMII1_TXC direction
[ Upstream commit 69db725cdb2b803af67897a08ea54467d11f6020 ]
The MCU RGMII MCU_RGMII1_TXC pin is defined as input by mistake, although
this does not make any difference functionality wise it's better to update
to avoid confusion.
Hence fix MCU RGMII MCU_RGMII1_TXC pin pinmux definitions to be an output
in K3 am654x/j721e/j7200 board files.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210526132041.6104-1-grygorii.strashko@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
|
Revision tags: v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13 |
|
| #
bbcb0522 |
| 30-Sep-2020 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
The board uses lane 3 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
The board uses lane 3 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, QSGMII and USB super-speed. It has been
chosen to use PCI2 and QSGMII as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-7-rogerq@ti.com
show more ...
|
| #
e38a45b0 |
| 30-Sep-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
show more ...
|
|
Revision tags: v5.8.12 |
|
| #
a2178b83 |
| 24-Sep-2020 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card
Add support for the eMMC and SD card connected on the common
processor board
sdhci0 is connected to an eMMC while sdhci1
arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card
Add support for the eMMC and SD card connected on the common
processor board
sdhci0 is connected to an eMMC while sdhci1 is connected to the
micro SD slot.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200924112644.11076-3-faiz_abbas@ti.com
show more ...
|
| #
e25889f8 |
| 23-Sep-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instances.
Signed-
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instances.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
Link: https://lore.kernel.org/r/20200923155400.13757-3-vigneshr@ti.com
show more ...
|
| #
fc3b1550 |
| 23-Sep-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs
The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.
Hence, ad
arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs
The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.
Hence, add pinmux and Ethernet PHY configuration for TI J7200 SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-5-grygorii.strashko@ti.com
show more ...
|
|
Revision tags: v5.8.11, v5.8.10 |
|
| #
26bd3f31 |
| 14-Sep-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: Add support for J7200 Common Processor Board
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+-------------------------------
arm64: dts: ti: Add support for J7200 Common Processor Board
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality.
Note:
* The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
* Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
* All daughter cards beyond the basic boards shall be maintained as
overlays.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-6-lokeshvutla@ti.com
show more ...
|
| #
c8815d6f |
| 26-May-2021 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-am654x/j721e/j7200-common-proc-board: Fix MCU_RGMII1_TXC direction
[ Upstream commit 69db725cdb2b803af67897a08ea54467d11f6020 ]
The MCU RGMII MCU_RGMII1_TXC pin i
arm64: dts: ti: k3-am654x/j721e/j7200-common-proc-board: Fix MCU_RGMII1_TXC direction
[ Upstream commit 69db725cdb2b803af67897a08ea54467d11f6020 ]
The MCU RGMII MCU_RGMII1_TXC pin is defined as input by mistake, although
this does not make any difference functionality wise it's better to update
to avoid confusion.
Hence fix MCU RGMII MCU_RGMII1_TXC pin pinmux definitions to be an output
in K3 am654x/j721e/j7200 board files.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210526132041.6104-1-grygorii.strashko@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
|
Revision tags: v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13 |
|
| #
bbcb0522 |
| 30-Sep-2020 |
Roger Quadros <rogerq@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
The board uses lane 3 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
The board uses lane 3 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, QSGMII and USB super-speed. It has been
chosen to use PCI2 and QSGMII as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-7-rogerq@ti.com
show more ...
|
| #
e38a45b0 |
| 30-Sep-2020 |
Kishon Vijay Abraham I <kishon@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is conn
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
show more ...
|
|
Revision tags: v5.8.12 |
|
| #
a2178b83 |
| 24-Sep-2020 |
Faiz Abbas <faiz_abbas@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card
Add support for the eMMC and SD card connected on the common
processor board
sdhci0 is connected to
arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card
Add support for the eMMC and SD card connected on the common
processor board
sdhci0 is connected to an eMMC while sdhci1 is connected to the
micro SD slot.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200924112644.11076-3-faiz_abbas@ti.com
show more ...
|
| #
e25889f8 |
| 23-Sep-2020 |
Vignesh Raghavendra <vigneshr@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instanc
arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instances.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
Link: https://lore.kernel.org/r/20200923155400.13757-3-vigneshr@ti.com
show more ...
|
| #
fc3b1550 |
| 23-Sep-2020 |
Grygorii Strashko <grygorii.strashko@ti.com> |
arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs
The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode
arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs
The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.
Hence, add pinmux and Ethernet PHY configuration for TI J7200 SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-5-grygorii.strashko@ti.com
show more ...
|
|
Revision tags: v5.8.11, v5.8.10 |
|
| #
26bd3f31 |
| 14-Sep-2020 |
Lokesh Vutla <lokeshvutla@ti.com> |
arm64: dts: ti: Add support for J7200 Common Processor Board
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+-----------
arm64: dts: ti: Add support for J7200 Common Processor Board
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality.
Note:
* The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
* Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
* All daughter cards beyond the basic boards shall be maintained as
overlays.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200914162231.2535-6-lokeshvutla@ti.com
show more ...
|