History log of /openbmc/linux/drivers/soc/imx/Makefile (Results 26 – 27 of 27)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
Revision tags: v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7
# 03aa1262 28-Mar-2017 Andrey Smirnov <andrew.smirnov@gmail.com>

soc: imx: Add GPCv2 power gating driver

Add code allowing for control of various power domains managed by GPCv2
IP block found in i.MX7 series of SoCs. Power domains covered by this

soc: imx: Add GPCv2 power gating driver

Add code allowing for control of various power domains managed by GPCv2
IP block found in i.MX7 series of SoCs. Power domains covered by this
patch are:

- PCIE PHY
- MIPI PHY
- USB HSIC PHY
- USB OTG1/2 PHY

Support for any other power domain controlled by GPC is not present, and
can be added at some later point.

Testing of this code was done against a PCIe driver.

Cc: yurovsky@gmail.com
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Dong Aisheng <dongas86@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Revision tags: v4.10.6, v4.10.5, v4.10.4, v4.10.3, v4.10.2, v4.10.1, v4.10
# 721cabf6 17-Feb-2017 Lucas Stach <l.stach@pengutronix.de>

soc: imx: move PGC handling to a new GPC driver

This is an almost complete re-write of the previous GPC power gating control
code found in the IMX architecture code. It supports both the

soc: imx: move PGC handling to a new GPC driver

This is an almost complete re-write of the previous GPC power gating control
code found in the IMX architecture code. It supports both the old and the new
DT binding, allowing more domains to be added later and generally makes the
driver easier to extend, while keeping compatibility with existing DTBs.

As the result, all functionality regarding the power gating controller
gets removed from the IMX architecture GPC driver. It keeps only the
IRQ controller code in the architecture, as this is closely coupled to
the CPU idle implementation.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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