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3bfd5f42 |
| 28-Oct-2020 |
Mark Brown <broonie@kernel.org> |
Merge tag 'v5.10-rc1' into spi-5.10
Linux 5.10-rc1
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ce038aea |
| 28-Oct-2020 |
Mark Brown <broonie@kernel.org> |
Merge tag 'v5.10-rc1' into asoc-5.10
Linux 5.10-rc1
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Revision tags: v5.8.16 |
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b4e1bce8 |
| 14-Oct-2020 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "Core changes:
- NONE whatsoever, we don't even to
Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "Core changes:
- NONE whatsoever, we don't even touch the core files this time around.
New drivers:
- New driver for the Toshiba Visconti SoC.
- New subdriver for the Qualcomm MSM8226 SoC.
- New subdriver for the Actions Semiconductor S500 SoC.
- New subdriver for the Mediatek MT8192 SoC.
- New subdriver for the Microchip SAMA7G5 SoC.
Driver enhancements:
- Intel Cherryview and Baytrail cleanups and refactorings.
- Enhanced support for the Renesas R8A7790, more pins and groups.
- Some optimizations for the MCP23S08 MCP23x17 variant.
- Some cleanups around the Actions Semiconductor subdrivers.
- A bunch of cleanups around the SH-PFC and Emma Mobile drivers.
- The "SH-PFC" (literally SuperH pin function controller, I think) subdirectory is now renamed to the more neutral "renesas", as these are not very much centered around SuperH anymore.
- Non-critical fixes for the Aspeed driver.
- Non-critical fixes for the Ingenic (MIPS!) driver.
- Fix a bunch of missing pins on the AMD pinctrl driver"
* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits) pinctrl: amd: Add missing pins to the pin group list dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI pinctrl: mediatek: Free eint data on failure pinctrl: single: fix debug output when #pinctrl-cells = 2 pinctrl: single: fix pinctrl_spec.args_count bounds check pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent pinctrl: cannonlake: Modify COMMUNITY macros to be consistent pinctrl: tigerlake: Fix register offsets for TGL-H variant pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2 pinctrl: mediatek: use devm_platform_ioremap_resource_byname() pinctrl: nuvoton: npcm7xx: Constify static ops structs pinctrl: mediatek: mt7622: add antsel pins/groups pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register() pinctrl: at91-pio4: add support for sama7g5 SoC dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5 pinctrl: spear: simplify the return expression of tvc_connect() pinctrl: spear: simplify the return expression of spear310_pinctrl_probe pinctrl: sprd: use module_platform_driver to simplify the code pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs. ...
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Revision tags: v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11 |
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e777f8c8 |
| 21-Sep-2020 |
Linus Walleij <linus.walleij@linaro.org> |
Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.10
- Add CAN and USB1 PWEN pin groups
Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.10
- Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1, - Three more conversion of DT bindings to json-schema, - Group all Renesas pinctrl drivers and improve visual Kconfig structure, - Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, - Minor fixes and improvements.
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Revision tags: v5.8.10, v5.8.9, v5.8.8 |
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540d9757 |
| 09-Sep-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc code
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: C
pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc code
Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not.
Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed.
This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be
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077365a9 |
| 09-Sep-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
pinctrl: Rename sh-pfc to renesas
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "s
pinctrl: Rename sh-pfc to renesas
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs.
Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS.
Rename the git branch in MAINTAINERS, too, for consistency.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
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