Revision tags: v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4, v4.1-rc3, v4.1-rc2, v4.1-rc1, v4.0 |
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#
57991eba |
| 07-Apr-2015 |
Andrew Bresticker <abrestic@chromium.org> |
PHY: Add driver for Pistachio USB2.0 PHY
Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Kishon Vijay Abraham I <kishon@
PHY: Add driver for Pistachio USB2.0 PHY
Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley <james.hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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#
10d9029b |
| 29-May-2015 |
Rob Herring <robh@kernel.org> |
phy: add Marvell HSIC 28nm PHY
Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928 SOC.
Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com
phy: add Marvell HSIC 28nm PHY
Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928 SOC.
Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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603c5f9d |
| 29-May-2015 |
Rob Herring <robh@kernel.org> |
phy: Add Marvell USB 2.0 OTG 28nm PHY
Add driver for USB 28nm PHY found in Marvell PXA1928 SOC.
Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by
phy: Add Marvell USB 2.0 OTG 28nm PHY
Add driver for USB 28nm PHY found in Marvell PXA1928 SOC.
Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
0d486806 |
| 20-May-2015 |
Brian Norris <computersforpeace@gmail.com> |
phy: add Broadcom SATA3 PHY driver for Broadcom STB SoCs
Supports up to two ports which can each be powered on/off and configured independently.
Signed-off-by: Brian Norris <computersforpeace@gmail
phy: add Broadcom SATA3 PHY driver for Broadcom STB SoCs
Supports up to two ports which can each be powered on/off and configured independently.
Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
1c14905e |
| 13-May-2015 |
Heikki Krogerus <heikki.krogerus@linux.intel.com> |
phy: add driver for TI TUSB1210 ULPI PHY
TUSB1210 ULPI PHY has vendor specific register for eye diagram tuning. On some platforms the system firmware has set optimized value to it. In order to not l
phy: add driver for TI TUSB1210 ULPI PHY
TUSB1210 ULPI PHY has vendor specific register for eye diagram tuning. On some platforms the system firmware has set optimized value to it. In order to not loose the optimized value, the driver stores it during probe and restores it every time the PHY is powered back on.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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Revision tags: v4.0-rc7, v4.0-rc6, v4.0-rc5, v4.0-rc4 |
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#
9c3b4430 |
| 13-Mar-2015 |
Chen-Yu Tsai <wens@csie.org> |
phy: Add driver to support individual USB PHYs on sun9i
Unlike previous Allwinner SoCs, there is no central PHY control block on the A80. Also, OTG support is completely split off into a different c
phy: Add driver to support individual USB PHYs on sun9i
Unlike previous Allwinner SoCs, there is no central PHY control block on the A80. Also, OTG support is completely split off into a different controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
609adde8 |
| 19-Mar-2015 |
Tony Lindgren <tony@atomide.com> |
phy: Add a driver for dm816x USB PHY
Add a minimal driver for dm816x USB. This makes USB work on dm816x without any other changes needed as it can use the existing musb_dsps glue layer for the USB c
phy: Add a driver for dm816x USB PHY
Add a minimal driver for dm816x USB. This makes USB work on dm816x without any other changes needed as it can use the existing musb_dsps glue layer for the USB controller.
Note that this phy is different from dm814x and am335x.
Cc: Bin Liu <binmlist@gmail.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Revision tags: v4.0-rc3, v4.0-rc2, v4.0-rc1, v3.19, v3.19-rc7, v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1 |
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#
64d11406 |
| 12-Dec-2014 |
Yunzhi Li <lyz@rock-chips.com> |
phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs, currently this driver can support RK3288. The RK3288 SoC have three independe
phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs, currently this driver can support RK3288. The RK3288 SoC have three independent USB PHY IPs which are all configured through a set of registers located in the GRF (general register files) module.
Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
ca14ab55 |
| 15-Jan-2015 |
Yaniv Gardi <ygardi@codeaurora.org> |
phy: qcom-ufs: add support for 14nm phy
This change adds a support for a 14nm qcom-ufs phy that is required in platforms that use ufs-qcom controller.
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.
phy: qcom-ufs: add support for 14nm phy
This change adds a support for a 14nm qcom-ufs phy that is required in platforms that use ufs-qcom controller.
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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#
39e794bf |
| 15-Jan-2015 |
Yaniv Gardi <ygardi@codeaurora.org> |
phy: qcom-ufs: add support for 20nm phy
This change adds a support for a 20nm qcom-ufs phy that is required in platforms that use ufs-qcom controller.
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.
phy: qcom-ufs: add support for 20nm phy
This change adds a support for a 20nm qcom-ufs phy that is required in platforms that use ufs-qcom controller.
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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#
adaafaa3 |
| 15-Jan-2015 |
Yaniv Gardi <ygardi@codeaurora.org> |
phy: qcom-ufs: add support for QUALCOMM Technologies UFS PHY drivers
This change adds a generic and common API support for ufs phy QUALCOMM Technologies. This support provides common code and also p
phy: qcom-ufs: add support for QUALCOMM Technologies UFS PHY drivers
This change adds a generic and common API support for ufs phy QUALCOMM Technologies. This support provides common code and also points to specific phy callbacks to differentiate between different behaviors of frequent use-cases (like power on, power off, phy calibration etc).
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
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Revision tags: v3.18, v3.18-rc7, v3.18-rc6, v3.18-rc5 |
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#
eee47538 |
| 13-Nov-2014 |
Gregory CLEMENT <gregory.clement@free-electrons.com> |
phy: add support for USB cluster on the Armada 375 SoC
The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage comm
phy: add support for USB cluster on the Armada 375 SoC
The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage common features of both USB controllers.
This commit adds a driver integrated in the generic PHY framework to control this USB cluster feature.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [ kishon@ti.com : Made it to use the updated devm_phy_create API and soem cosmentic changes in Kconfig file.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
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#
13ebb68c |
| 20-Nov-2014 |
Antoine Tenart <antoine.tenart@free-electrons.com> |
phy: add the Berlin USB PHY driver
Add the driver driving the Marvell Berlin USB PHY. This allows to initialize the PHY and to use it from the USB driver later.
Signed-off-by: Antoine Tenart <antoi
phy: add the Berlin USB PHY driver
Add the driver driving the Marvell Berlin USB PHY. This allows to initialize the PHY and to use it from the USB driver later.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Revision tags: v3.18-rc4 |
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#
2c14e9be |
| 04-Nov-2014 |
Gabriel FERNANDEZ <gabriel.fernandez@st.com> |
phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices.
Signed-off-by: alexandre torgue <alexandre.torgue@
phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY
The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices.
Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Revision tags: v3.18-rc3, v3.18-rc2, v3.18-rc1, v3.17, v3.17-rc7, v3.17-rc6, v3.17-rc5 |
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#
3f8da2e3 |
| 08-Sep-2014 |
Peter Griffin <peter.griffin@linaro.org> |
phy: phy-stih41x-usb: Add usb phy support for STiH41x SoCs.
This driver adds support for USB (1.1 and 2.0) phy for STiH415 and STiH416 System-On-Chips from STMicroelectronics.
Signed-off-by: Maxime
phy: phy-stih41x-usb: Add usb phy support for STiH41x SoCs.
This driver adds support for USB (1.1 and 2.0) phy for STiH415 and STiH416 System-On-Chips from STMicroelectronics.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
89ae1f5d |
| 11-Sep-2014 |
Peter Griffin <peter.griffin@linaro.org> |
phy: phy-stih407-usb: Add usb picoPHY driver found on stih407 SoC family
This is the generic phy driver for the picoPHY ports used by the USB2 and USB3 Host controllers when controlling usb2/1.1 dev
phy: phy-stih407-usb: Add usb picoPHY driver found on stih407 SoC family
This is the generic phy driver for the picoPHY ports used by the USB2 and USB3 Host controllers when controlling usb2/1.1 devices. It is found on STiH407 SoC family from STMicroelectronics.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Revision tags: v3.17-rc4, v3.17-rc3, v3.17-rc2, v3.17-rc1, v3.16, v3.16-rc7 |
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#
1233f59f |
| 22-Jul-2014 |
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
phy: Renesas R-Car Gen2 PHY driver
This PHY, though formally being a part of Renesas USBHS controller, contains the UGCTRL2 register that controls multiplexing of the USB ports (Renesas calls them c
phy: Renesas R-Car Gen2 PHY driver
This PHY, though formally being a part of Renesas USBHS controller, contains the UGCTRL2 register that controls multiplexing of the USB ports (Renesas calls them channels) to the different USB controllers: channel 0 can be connected to either PCI EHCI/OHCI or USBHS controllers, channel 2 can be connected to PCI EHCI/OHCI or xHCI controllers.
This is a new driver for this USB PHY currently already supported under drivers/ usb/phy/. The reason for writing the new driver was the requirement that the multiplexing of USB channels to the controller be dynamic, depending on what USB drivers are loaded, rather than static as provided by the old driver. The infrastructure provided by drivers/phy/phy-core.c seems to fit that purpose ideally. The new driver only supports device tree probing for now.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Revision tags: v3.16-rc6, v3.16-rc5 |
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#
6e877fed |
| 09-Jul-2014 |
Lee Jones <lee.jones@linaro.org> |
phy: miphy365x: Provide support for the MiPHY356x Generic PHY
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both
phy: miphy365x: Provide support for the MiPHY356x Generic PHY
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration.
Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
4f6160d4 |
| 16-Jul-2014 |
Kumar Gala <galak@codeaurora.org> |
phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala <galak@codeaurora.org> Sign
phy: qcom: Add driver for QCOM IPQ806x SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
942a31b5 |
| 07-Jul-2014 |
Antoine Ténart <antoine.tenart@free-electrons.com> |
phy: add a driver for the Berlin SATA PHY
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.
The mode selection can let us think this PHY can be configured to fit other purposes.
phy: add a driver for the Berlin SATA PHY
The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.
The mode selection can let us think this PHY can be configured to fit other purposes. But there are reasons to think the SATA mode will be the only one usable: the PHY registers are only accessible indirectly through two registers in the SATA range, the PHY seems to be integrated and no information tells us the contrary. For these reasons, make the driver a SATA PHY driver.
Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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#
1de990d8 |
| 14-Jul-2014 |
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> |
phy: qcom: Add driver for QCOM APQ8064 SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the APQ8064 family of SoCs.
This patch is a forward port from Qualcomm's v3.4 and
phy: qcom: Add driver for QCOM APQ8064 SATA PHY
Add a PHY driver for uses with AHCI based SATA controller driver on the APQ8064 family of SoCs.
This patch is a forward port from Qualcomm's v3.4 andriod kernel.
Tested on IFC6410 board.
CC: Sujit Reddy Thumma <sthumma@codeaurora.org> Tested-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Revision tags: v3.16-rc4 |
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#
e379413a |
| 03-Jul-2014 |
Jiancheng Xue <xuejiancheng@huawei.com> |
phy: add hix5hd2-sata-phy driver
Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> S
phy: add hix5hd2-sata-phy driver
Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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Revision tags: v3.16-rc3, v3.16-rc2, v3.16-rc1, v3.15, v3.15-rc8, v3.15-rc7, v3.15-rc6, v3.15-rc5, v3.15-rc4, v3.15-rc3, v3.15-rc2, v3.15-rc1, v3.14, v3.14-rc8, v3.14-rc7, v3.14-rc6, v3.14-rc5, v3.14-rc4, v3.14-rc3, v3.14-rc2, v3.14-rc1, v3.13, v3.13-rc8, v3.13-rc7, v3.13-rc6, v3.13-rc5 |
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#
949ccc3a |
| 20-Dec-2013 |
Mateusz Krawczuk <mat.krawczuk@gmail.com> |
phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver
Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver.
Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung
phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver
Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver.
Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> [k.debski@samsung.com: cleanup and commit description] [k.debski@samsung.com: make changes accordingly to the mailing list comments] Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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#
64562e99 |
| 14-Apr-2014 |
Pratyush Anand <pratyush.anand@st.com> |
phy: Add drivers for PCIe and SATA phy on SPEAr13xx
ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphy
phy: Add drivers for PCIe and SATA phy on SPEAr13xx
ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.
This also adds proper bindings for miphys.
Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Tested-by: Mohit Kumar <mohit.kumar@st.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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#
59025887 |
| 13-May-2014 |
Vivek Gautam <gautam.vivek@samsung.com> |
phy: Add new Exynos5 USB 3.0 PHY driver
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present o
phy: Add new Exynos5 USB 3.0 PHY driver
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs.
Also, created a new header file in linux/mfd/syscon/ for Exynos5 SoCs and put the required PMU offset definitions for the basic available PHYs.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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