Revert "phy: Add USB3 PHY support for Broadcom NSP SoC"

This reverts commit d7bc1a7d41bf ("phy: Add USB3 PHY support for
Broadcom NSP SoC") as we already have driver for this PHY (shared by NS
and N

Revert "phy: Add USB3 PHY support for Broadcom NSP SoC"

This reverts commit d7bc1a7d41bf ("phy: Add USB3 PHY support for
Broadcom NSP SoC") as we already have driver for this PHY (shared by NS
and NSP). It was added in commit e5666281d9ea ("phy: bcm-ns-usb3: new
driver for USB 3.0 PHY on Northstar").

Instead of adding separated driver & duplicating code we should work on
improving existing (old) one. Thanks to work done by Broadcom we know
there is MDIO bus we weren't aware of & we know register names which
makes initialization more clear. This is very valuable info and we
should work on using it in existing driver afterwards.

Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>

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phy: phy-exynos-pcie: Add support for Exynos PCIe PHY

Add support for Generic PHY framework about Exynos SoCs. Current Exynos
PCIe driver doesn't use the PHY framework, which makes it difficult to

phy: phy-exynos-pcie: Add support for Exynos PCIe PHY

Add support for Generic PHY framework about Exynos SoCs. Current Exynos
PCIe driver doesn't use the PHY framework, which makes it difficult to
upstream the other Exynos variants because of different PHY registers.

Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
driver.

[bhelgaas: depend on "OF && (ARCH_EXYNOS || COMPILE_TEST)", update
copyright year, both per Vivek]
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

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phy: Add USB3 PHY support for Broadcom NSP SoC

This patch adds support for Broadcom NSP USB3 PHY

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Reviewed-by: Floria

phy: Add USB3 PHY support for Broadcom NSP SoC

This patch adds support for Broadcom NSP USB3 PHY

Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: Add support for Qualcomm's USB HS phy

The high-speed phy on qcom SoCs is controlled via the ULPI
viewport.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: <devicetree@vger.kernel.org>
Acked-by:

phy: Add support for Qualcomm's USB HS phy

The high-speed phy on qcom SoCs is controlled via the ULPI
viewport.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: <devicetree@vger.kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: Add support for Qualcomm's USB HSIC phy

The HSIC USB controller on qcom SoCs has an integrated all
digital phy controlled via the ULPI viewport.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acke

phy: Add support for Qualcomm's USB HSIC phy

The HSIC USB controller on qcom SoCs has an integrated all
digital phy controlled via the ULPI viewport.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: stih41x-usb: Remove usb phy driver and dt binding
documentation.

This phy is only used on STiH415/6 based silicon, and support for
these SoC's is being removed from the kernel.

Signed-off-by:

phy: stih41x-usb: Remove usb phy driver and dt binding
documentation.

This phy is only used on STiH415/6 based silicon, and support for
these SoC's is being removed from the kernel.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: phy-miphy365x: Remove miphy365 driver and dt binding
documentation.

This phy is only used on STiH415/6 based silicon, and support for
these SoC's is being removed from the kernel.

Signed-off-

phy: phy-miphy365x: Remove miphy365 driver and dt binding
documentation.

This phy is only used on STiH415/6 based silicon, and support for
these SoC's is being removed from the kernel.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: meson: add USB2 PHY support for Meson8b and GXBB

This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Si

phy: meson: add USB2 PHY support for Meson8b and GXBB

This is a new driver for the USB PHY found in Meson8b and GXBB SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: Add USB Type-C PHY driver for rk3399

Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications.
The USB3 operates in SuperS

phy: Add USB Type-C PHY driver for rk3399

Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB
Type-C PHY is designed to support the USB3 and DP applications.
The USB3 operates in SuperSpeed mode and the DP can operate at RBR,
HBR and HBR2 data rates. This driver create 2 PHY devices separately
for USB3 and DisplyPort, and registers them under the child node.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: add a driver for the Rockchip SoC internal PCIe PHY

This patch to add a generic PHY driver for rockchip PCIe PHY.
Access the PHY via registers provided by GRF (general register
files) module.

phy: add a driver for the Rockchip SoC internal PCIe PHY

This patch to add a generic PHY driver for rockchip PCIe PHY.
Access the PHY via registers provided by GRF (general register
files) module.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: rockchip-inno-usb2: add a new driver for Rockchip usb2phy

The newer SoCs (rk3366, rk3399) take a different usb-phy IP block
than rk3288 and before, and most of phy-related registers are also
di

phy: rockchip-inno-usb2: add a new driver for Rockchip usb2phy

The newer SoCs (rk3366, rk3399) take a different usb-phy IP block
than rk3288 and before, and most of phy-related registers are also
different from the past, so a new phy driver is required necessarily.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Suggested-by: Guenter Roeck <linux@roeck-us.net>
Suggested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar

Northstar is a family of SoCs used in home routers. They have USB 2.0
and 3.0 controllers with PHYs that need to be properly initialized.
Th

phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar

Northstar is a family of SoCs used in home routers. They have USB 2.0
and 3.0 controllers with PHYs that need to be properly initialized.
This driver provides PHY init support in a generic way and can be bound
with XHCI controller driver.

There aren't any public datasheets from Broadcom so we can't have nice
defines for all used bits. It means we just follow Broadcom's
initialization procedure using their magic values. We were quite lucky
actually that Broadcom put some comments in their SDK reference code
explaining what given writes are responsible for.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: da8xx-usb: new driver for DA8xx SoC USB PHY

This is a new phy driver for the SoC USB controllers on the TI DA8xx
family of microcontrollers. The USB 1.1 PHY is just a simple on/off.
The USB 2.0

phy: da8xx-usb: new driver for DA8xx SoC USB PHY

This is a new phy driver for the SoC USB controllers on the TI DA8xx
family of microcontrollers. The USB 1.1 PHY is just a simple on/off.
The USB 2.0 PHY also allows overriding the VBUS and ID pins.

Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: Add Northstar2 PCI Phy support

Add PCI Phy support for Broadcom Northstar2 SoCs. This driver uses the
interface from the iproc mdio mux driver to enable the devices
respective phys.

Reviewed-

phy: Add Northstar2 PCI Phy support

Add PCI Phy support for Broadcom Northstar2 SoCs. This driver uses the
interface from the iproc mdio mux driver to enable the devices
respective phys.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar

Northstar is a family of SoCs used in home routers. They have USB 2.0
and 3.0 controllers with PHYs that need to be properly initialized.
Th

phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar

Northstar is a family of SoCs used in home routers. They have USB 2.0
and 3.0 controllers with PHYs that need to be properly initialized.
This driver provides PHY init support in a generic way and can be bound
with an EHCI controller driver.
There are (just a few) registers being defined in bcma header. It's
because DMU/CRU registers will be also needed in other drivers. We will
need them e.g. in PCIe controller/PHY driver and at some point probably
in clock driver for BCM53573 chipset. By using include/linux/bcma/ we
avoid code duplication.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: Add support for NS2 SATA3 PHY in Broadcom SATA3 PHY driver

This patch adds support for Broadcom NS2 SATA3 PHY in existing
Broadcom SATA3 PHY driver.

Signed-off-by: Anup Patel <anup.patel@broad

phy: Add support for NS2 SATA3 PHY in Broadcom SATA3 PHY driver

This patch adds support for Broadcom NS2 SATA3 PHY in existing
Broadcom SATA3 PHY driver.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: Add Tegra XUSB pad controller support

Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs.
This hardware block used to be exposed as a pin controller, but it turns
out that

phy: Add Tegra XUSB pad controller support

Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs.
This hardware block used to be exposed as a pin controller, but it turns
out that this isn't a good fit. The new driver and DT binding much more
accurately describe the hardware and are more flexible in supporting new
SoC generations.

Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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phy: Rename phy-brcmstb-sata driver to phy-brcm-sata driver

Currently, we have a common SATA3 PHY driver for all Broadcom
STB SoCs. This driver can be extended and re-used for Broadcom
iProc SoCs ha

phy: Rename phy-brcmstb-sata driver to phy-brcm-sata driver

Currently, we have a common SATA3 PHY driver for all Broadcom
STB SoCs. This driver can be extended and re-used for Broadcom
iProc SoCs having same SATA3 PHY.

This patch renames existing Broadcom STB SATA3 PHY driver to
common Broadcom SATA3 PHY driver to share this PHY driver across
Broadcom SoCs.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: Add driver for rockchip Display Port PHY

Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.

Signed-off-by: Yakir Yang <ykk@ro

phy: Add driver for rockchip Display Port PHY

Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: add a driver for the Rockchip SoC internal eMMC PHY

This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
Access the PHY via registers provided by GRF (general register
files) module.

phy: add a driver for the Rockchip SoC internal eMMC PHY

This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
Access the PHY via registers provided by GRF (general register
files) module.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: add phy-hi6220-usb

Support hi6220 use phy for HiKey board

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <k

phy: add phy-hi6220-usb

Support hi6220 use phy for HiKey board

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver

This patch adds support for R-Car generation 3 USB2 PHY driver.
This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
with the HSUSB (USB

phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver

This patch adds support for R-Car generation 3 USB2 PHY driver.
This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
with the HSUSB (USB2.0 peripheral) device. And each channel has
independent registers about the PHYs.

So, the purpose of this driver is:
1) initializes some registers of SoC specific to use the
{ehci,ohci}-platform driver.

2) detects id pin to select host or peripheral on the channel 0.

For now, this driver only supports 1) above.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: cygnus: pcie: Add Cygnus PCIe PHY support

This patch adds the PCIe PHY support for the Broadcom PCIe RC interface
on Cygnus

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parames

phy: cygnus: pcie: Add Cygnus PCIe PHY support

This patch adds the PCIe PHY support for the Broadcom PCIe RC interface
on Cygnus

Signed-off-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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phy: add usb3.0 phy driver for mt65xx SoCs

support usb3.0 phy of mt65xx SoCs

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

phy: add lpc18xx usb otg phy driver

Add PHY driver for the internal USB OTG PHY found on NXP
LPC18xx and LPC43xx devices. This driver takes care of
enabling the PHY in CREG (syscon) and setting the

phy: add lpc18xx usb otg phy driver

Add PHY driver for the internal USB OTG PHY found on NXP
LPC18xx and LPC43xx devices. This driver takes care of
enabling the PHY in CREG (syscon) and setting the required
clock frequency.

Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

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