Revision tags: v5.10.51, v5.10.50, v5.10.49 |
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#
6f14078e |
| 30-Jun-2021 |
Sunil Kumar Kori <skori@marvell.com> |
octeontx2-af: DMAC filter support in MAC block
MAC block supports 32 dmac filters which are logically divided among all attached LMACS.
For example MAC block0 having one LMAC then maximum supported
octeontx2-af: DMAC filter support in MAC block
MAC block supports 32 dmac filters which are logically divided among all attached LMACS.
For example MAC block0 having one LMAC then maximum supported filters are 32 where as MAC block1 having 4 enabled LMACS them maximum supported filteres are 8 for each LMAC.
This patch adds mbox handlers to add/delete/update mac entry in DMAC filter table.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.13, v5.10.46 |
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#
e7d89717 |
| 15-Jun-2021 |
Sunil Goutham <sgoutham@marvell.com> |
octeontx2-af: cn10k: Debugfs support for bandwidth profiles
Added support for dumping current resource status of bandwidth profiles and contexts of allocated profiles via debugfs.
Signed-off-by: Su
octeontx2-af: cn10k: Debugfs support for bandwidth profiles
Added support for dumping current resource status of bandwidth profiles and contexts of allocated profiles via debugfs.
Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
e8e095b3 |
| 15-Jun-2021 |
Sunil Goutham <sgoutham@marvell.com> |
octeontx2-af: cn10k: Bandwidth profiles config support
CN10K silicons supports hierarchial ingress packet ratelimiting. There are 3 levels of profilers supported leaf, mid and top. Ratelimiting is d
octeontx2-af: cn10k: Bandwidth profiles config support
CN10K silicons supports hierarchial ingress packet ratelimiting. There are 3 levels of profilers supported leaf, mid and top. Ratelimiting is done after packet forwarding decision is taken and a NIXLF's RQ is identified to DMA the packet. RQ's context points to a leaf bandwidth profile which can be configured to achieve desired ratelimit.
This patch adds logic for management of these bandwidth profiles ie profile alloc, free, context update etc.
Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
bd4302b8 |
| 11-Jun-2021 |
Hariprasad Kelam <hkelam@marvell.com> |
octeontx2-af: add new mailbox to configure VF trust mode
Add new mailbox to enable PF to configure VF as trusted VF. Trusted VF feature allows VFs to perform priviliged operations such as enabling V
octeontx2-af: add new mailbox to configure VF trust mode
Add new mailbox to enable PF to configure VF as trusted VF. Trusted VF feature allows VFs to perform priviliged operations such as enabling VF promiscuous mode, all-multicast mode and changing the VF MAC address configured by PF. Refactored the VF interface flags maintained by the AF driver such that the flags do not overlap for various configurations.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
967db352 |
| 11-Jun-2021 |
Naveen Mamindlapalli <naveenm@marvell.com> |
octeontx2-af: add support for multicast/promisc packet replication feature
Currently, multicast packet filtering is accomplished by installing MCAM rule that matches all-multicast MAC address and ha
octeontx2-af: add support for multicast/promisc packet replication feature
Currently, multicast packet filtering is accomplished by installing MCAM rule that matches all-multicast MAC address and has its NPC_RX_ACTION set to unicast to PF. Similarly promisc feature is achieved by installing MCAM rule that matches all the traffic received by the channel and unicast the packets to PF. This approach only applies to PF and is not scalable across VFs.
This patch adds support for PF/VF multicast and promisc feature by reserving NIX_RX_MCE_S entries from the global MCE list allocated during NIX block initialization. The NIX_RX_MCE_S entries create a linked list with a flag indicating the end of the list, and each entry points to a PF_FUNC (either PF or VF). When a packet NPC_RX_ACTION is set to MCAST, the corresponding NIX_RX_MCE_S list is traversed and the packet is queued to each PF_FUNC available on the list.
The PF or VF driver adds the multicast/promisc packet match entry and updates the MCE list with correspondng PF_FUNC. When a PF or VF interface is disabled, the corresponding NIX_RX_MCE_S entry is removed from the MCE list and the MCAM entry will be disabled if the list is empty.
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.10.43, v5.10.42, v5.10.41 |
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#
c87e6b13 |
| 27-May-2021 |
Harman Kalra <hkalra@marvell.com> |
octeontx2-af: adding new lt def registers support
CN10k introduces following new LT DEF registers: 1. APAD (alignment padding) LT DEF registers are enhancement to existing apad calculation algorithm
octeontx2-af: adding new lt def registers support
CN10k introduces following new LT DEF registers: 1. APAD (alignment padding) LT DEF registers are enhancement to existing apad calculation algorithm where not just ipv4 and ipv6 but also other protocols can be matched and required alignment can be added by NIX.
2. ET LT DEF register defines layer information in NPC_RESULT_S to identify the Ethertype location in L2 header. Used for Ethertype overwriting in inline IPsec flow.
This patch adds required structures and some header changes. Also strict version check (based on minor field) is imposed to highlight version mismatch between the kernel headers and KPU profile.
Signed-off-by: Harman Kalra <hkalra@marvell.com> Signed-off-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com> Signed-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Revision tags: v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25 |
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#
8c16cb03 |
| 18-Mar-2021 |
Subbaraya Sundeep <sbhatta@marvell.com> |
octeontx2-af: Fix uninitialized variable warning
Initialize l4_key_offset variable to fix uninitialized variable compiler warning.
Fixes: b9b7421a01d8 ("octeontx2-af: Support ESP/AH RSS hashing") S
octeontx2-af: Fix uninitialized variable warning
Initialize l4_key_offset variable to fix uninitialized variable compiler warning.
Fixes: b9b7421a01d8 ("octeontx2-af: Support ESP/AH RSS hashing") Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.10.24 |
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#
b6b0e366 |
| 17-Mar-2021 |
Subbaraya Sundeep <sbhatta@marvell.com> |
octeontx2-af: Avoid duplicate unicast rule in mcam_rules list
A mcam rule described by mcam_rule struct has all the info such as the hardware MCAM entry number, match criteria and corresponding acti
octeontx2-af: Avoid duplicate unicast rule in mcam_rules list
A mcam rule described by mcam_rule struct has all the info such as the hardware MCAM entry number, match criteria and corresponding action etc. All mcam rules are stored in a linked list mcam->rules. When adding/updating a rule to the mcam->rules it is checked if a rule already exists for the mcam entry. If the rule already exists, the same rule is updated instead of creating new rule. This way only one mcam_rule exists for the only one default unicast entry installed by AF. But a PF/VF can get different NIXLF (or default unicast entry number) after a attach-detach-attach sequence. When that happens mcam_rules list end up with two default unicast rules. Fix the problem by deleting the default unicast rule list node always when disabling mcam rules.
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
d450a235 |
| 17-Mar-2021 |
Nalla, Pradeep <pnalla@marvell.com> |
octeontx2-af: Add support for multi channel in NIX promisc entry
This patch adds support for multi channel NIX promisc entry. Packets sent on all those channels by the host should be received by the
octeontx2-af: Add support for multi channel in NIX promisc entry
This patch adds support for multi channel NIX promisc entry. Packets sent on all those channels by the host should be received by the interface to which those channels belong. Channel count, if greater than 1, should be power of 2 as only one promisc entry is available for the interface. Key mask is modified such that incoming packets from channel base to channel count are directed to the same pci function.
Signed-off-by: Nalla, Pradeep <pnalla@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16 |
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#
1845ada4 |
| 11-Feb-2021 |
Rakesh Babu <rsaladi2@marvell.com> |
octeontx2-af: cn10k: Add RPM LMAC pause frame support
Flow control configuration is different for CGX(Octeontx2) and RPM(CN10K) functional blocks. This patch adds the necessary changes for RPM to su
octeontx2-af: cn10k: Add RPM LMAC pause frame support
Flow control configuration is different for CGX(Octeontx2) and RPM(CN10K) functional blocks. This patch adds the necessary changes for RPM to support 802.3 pause frames configuration on cn10k platforms.
Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
6e54e1c5 |
| 11-Feb-2021 |
Hariprasad Kelam <hkelam@marvell.com> |
octeontx2-af: cn10K: Add MTU configuration
OcteonTx3 CN10K silicon supports bigger MTU when compared to 9216 MTU supported by OcteonTx2 silicon variants. Lookback interface supports upto 64K and RPM
octeontx2-af: cn10K: Add MTU configuration
OcteonTx3 CN10K silicon supports bigger MTU when compared to 9216 MTU supported by OcteonTx2 silicon variants. Lookback interface supports upto 64K and RPM LMAC interfaces support upto 16K.
This patch does the necessary configuration and adds support for PF/VF drivers to retrieve max packet size supported via mbox
This patch also configures tx link credit by considering supported fifo size and max packet length for Octeontx3 silicon.
This patch also removes platform specific name from the driver name.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
242da439 |
| 11-Feb-2021 |
Subbaraya Sundeep <sbhatta@marvell.com> |
octeontx2-af: cn10k: Add support for programmable channels
NIX uses unique channel numbers to identify the packet sources/sinks like CGX,LBK and SDP. The channel numbers assigned to each block are h
octeontx2-af: cn10k: Add support for programmable channels
NIX uses unique channel numbers to identify the packet sources/sinks like CGX,LBK and SDP. The channel numbers assigned to each block are hardwired in CN9xxx silicon. The fixed channel numbers in CN9xxx are:
0x0 | a << 8 | b - LBK(0..3)_CH(0..63) 0x0 | a << 8 - Reserved 0x700 | a - SDP_CH(0..255) 0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15)
All the channels in the above fixed enumerator(with maximum number of blocks) are not required since some chips have less number of blocks. For CN10K silicon the channel numbers need to be programmed by software in each block with the base channel number and range of channels. This patch calculates and assigns the channel numbers to efficiently distribute the channel number range(0-4095) among all the blocks. The assignment is made based on the actual number of blocks present and also contiguously leaving no holes. The channel numbers remaining after the math are used as new CPT replay channels present in CN10K. Also since channel numbers are not fixed the transmit channel link number needed by AF consumers is calculated by AF and sent along with nix_lf_alloc mailbox response.
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
91c6945e |
| 11-Feb-2021 |
Hariprasad Kelam <hkelam@marvell.com> |
octeontx2-af: cn10k: Add RPM MAC support
OcteonTx2's next gen platform the CN10K has RPM MAC which has a different serdes when compared to CGX MAC. Though the underlying HW is different, the CSR int
octeontx2-af: cn10k: Add RPM MAC support
OcteonTx2's next gen platform the CN10K has RPM MAC which has a different serdes when compared to CGX MAC. Though the underlying HW is different, the CSR interface has been designed largely inline with CGX MAC, with few exceptions though. So we are using the same CGX driver for RPM MAC as well and will have a different set of APIs for RPM where ever necessary.
This patch adds initial support for CN10K's RPM MAC i.e. the driver registration, communication with firmware etc. For communication with firmware, RPM provides a different IRQ when compared to CGX. The CGX and RPM blocks support different features. Currently few features like ptp, flowcontrol and higig are not supported by RPM. This patch adds new mailbox message "CGX_FEATURES_GET" to get the list of features supported by underlying MAC.
RPM has different implementations for RX/TX stats. Unlike CGX, bar offset of stat registers are different. This patch adds support to access the same and dump the values in debugfs.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
30077d21 |
| 11-Feb-2021 |
Geetha sowjanya <gakula@marvell.com> |
octeontx2-af: cn10k: Update NIX/NPA context structure
NIX hardware context structure got changed to accommodate new features like bandwidth steering, L3/L4 outer/inner checksum enable/disable etc.,
octeontx2-af: cn10k: Update NIX/NPA context structure
NIX hardware context structure got changed to accommodate new features like bandwidth steering, L3/L4 outer/inner checksum enable/disable etc., on CN10K platform. This patch defines new mbox message NIX_CN10K_AQ_INST for new NIX context initialization.
This patch also updates the NPA context structures to accommodate bit field changes made for CN10K platform.
This patch also removes Big endian bit fields from existing structures as its support got deprecated in current and upcoming silicons.
Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.10.15, v5.10.14 |
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#
b9b7421a |
| 22-Jan-2021 |
Subbaraya Sundeep <sbhatta@marvell.com> |
octeontx2-af: Support ESP/AH RSS hashing
Support SPI and sequence number fields of ESP/AH header to be hashed for RSS. By default ESP/AH fields are not considered for RSS and needs to be set explici
octeontx2-af: Support ESP/AH RSS hashing
Support SPI and sequence number fields of ESP/AH header to be hashed for RSS. By default ESP/AH fields are not considered for RSS and needs to be set explicitly as below: ethtool -U eth0 rx-flow-hash esp4 sdfn or ethtool -U eth0 rx-flow-hash ah4 sdfn or ethtool -U eth0 rx-flow-hash esp6 sdfn or ethtool -U eth0 rx-flow-hash ah6 sdfn
To disable hashing of ESP fields: ethtool -U eth0 rx-flow-hash esp4 sd or ethtool -U eth0 rx-flow-hash ah4 sd or ethtool -U eth0 rx-flow-hash esp6 sd or ethtool -U eth0 rx-flow-hash ah6 sd
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Link: https://lore.kernel.org/r/1611378552-13288-1-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Revision tags: v5.10 |
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#
f9e425e9 |
| 20-Nov-2020 |
George Cherian <george.cherian@marvell.com> |
octeontx2-af: Add support for RSS hashing based on Transport protocol field
Add support to choose RSS flow key algorithm with IPv4 transport protocol field included in hashing input data. This will
octeontx2-af: Add support for RSS hashing based on Transport protocol field
Add support to choose RSS flow key algorithm with IPv4 transport protocol field included in hashing input data. This will be enabled by default. There-by enabling 3/5 tuple hash
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Link: https://lore.kernel.org/r/20201120093906.2873616-1-george.cherian@marvell.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
dd6028a3 |
| 18-Nov-2020 |
Colin Ian King <colin.king@canonical.com> |
octeontx2-af: Fix return of uninitialized variable err
Currently the variable err may be uninitialized if several of the if statements are not executed in function nix_tx_vtag_decfg and a garbage va
octeontx2-af: Fix return of uninitialized variable err
Currently the variable err may be uninitialized if several of the if statements are not executed in function nix_tx_vtag_decfg and a garbage value in err is returned. Fix this by initialized ret at the start of the function.
Addresses-Coverity: ("Uninitialized scalar variable") Fixes: 9a946def264d ("octeontx2-af: Modify nix_vtag_cfg mailbox to support TX VTAG entries") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20201118132502.461098-1-colin.king@canonical.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
5a579667 |
| 14-Nov-2020 |
Subbaraya Sundeep <sbhatta@marvell.com> |
octeontx2-af: Delete NIX_RXVLAN_ALLOC mailbox message
Since mailbox message for installing flows is in place, remove the RXVLAN_ALLOC mbox message which is redundant.
Signed-off-by: Subbaraya Sunde
octeontx2-af: Delete NIX_RXVLAN_ALLOC mailbox message
Since mailbox message for installing flows is in place, remove the RXVLAN_ALLOC mbox message which is redundant.
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
4f88ed2c |
| 14-Nov-2020 |
Hariprasad Kelam <hkelam@marvell.com> |
octeontx2-af: Handle PF-VF mac address changes
This patch handles the VF mac address changes as given below. 1. mac addr configrued by VF will be retained until VF module unload. 2. mac addr
octeontx2-af: Handle PF-VF mac address changes
This patch handles the VF mac address changes as given below. 1. mac addr configrued by VF will be retained until VF module unload. 2. mac addr configred by PF for VF will be retained until power cycle. 3. mac addr confgired by PF for its VF can't be overwritten by VF.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
f0c2982a |
| 14-Nov-2020 |
Naveen Mamindlapalli <naveenm@marvell.com> |
octeontx2-pf: Add support for SR-IOV management functions
This patch adds support for ndo_set_vf_mac, ndo_set_vf_vlan and ndo_get_vf_config handlers. The traffic redirection based on the VF mac addr
octeontx2-pf: Add support for SR-IOV management functions
This patch adds support for ndo_set_vf_mac, ndo_set_vf_vlan and ndo_get_vf_config handlers. The traffic redirection based on the VF mac address or vlan id is done by installing MCAM rules. Reserved RX_VTAG_TYPE7 in each NIXLF for VF VLAN which strips the VLAN tag from ingress VLAN traffic. The NIX PF allocates two MCAM entries for VF VLAN feature, one used for ingress VTAG strip and another entry for egress VTAG insertion.
This patch also updates the MAC address in PF installed VF VLAN rule upon receiving nix_lf_start_rx mbox request for VF since Administrative Function driver will assign a valid MAC addr in nix_lf_start_rx function.
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Co-developed-by: Tomasz Duszynski <tduszynski@marvell.com> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
fd9d7859 |
| 14-Nov-2020 |
Hariprasad Kelam <hkelam@marvell.com> |
octeontx2-pf: Implement ingress/egress VLAN offload
This patch implements egress VLAN offload by appending NIX_SEND_EXT_S header to NIX_SEND_HDR_S. The VLAN TCI information is specified in the NIX_S
octeontx2-pf: Implement ingress/egress VLAN offload
This patch implements egress VLAN offload by appending NIX_SEND_EXT_S header to NIX_SEND_HDR_S. The VLAN TCI information is specified in the NIX_SEND_EXT_S. The VLAN offload in the ingress path is implemented by configuring the NIX_RX_VTAG_ACTION_S to strip and capture the outer vlan fields. The NIX PF allocates one MCAM entry for Rx VLAN offload.
Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
9a946def |
| 14-Nov-2020 |
Vamsi Attunuru <vattunuru@marvell.com> |
octeontx2-af: Modify nix_vtag_cfg mailbox to support TX VTAG entries
This patch modifies the existing nix_vtag_config mailbox message to allocate and free TX VTAG entries as requested by a NIX PF. T
octeontx2-af: Modify nix_vtag_cfg mailbox to support TX VTAG entries
This patch modifies the existing nix_vtag_config mailbox message to allocate and free TX VTAG entries as requested by a NIX PF. The TX VTAG entries are global resource that shared by all PFs and each entry specifies the size of VTAG to insert and the VTAG header data to insert. The mailbox response contains the entry index which is used by mailbox requester in configuring the NPC_TX_VTAG_ACTION for any MCAM entry.
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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#
55307fcb |
| 14-Nov-2020 |
Subbaraya Sundeep <sbhatta@marvell.com> |
octeontx2-af: Add mbox messages to install and delete MCAM rules
Added new mailbox messages to install and delete MCAM rules. These mailbox messages will be used for adding/deleting ethtool n-tuple
octeontx2-af: Add mbox messages to install and delete MCAM rules
Added new mailbox messages to install and delete MCAM rules. These mailbox messages will be used for adding/deleting ethtool n-tuple filters by NIX PF. The installed MCAM rules are stored in a list that will be traversed later to delete the MCAM entries when the interface is brought down or when PCIe FLR is received. The delete mailbox supports deleting a single MCAM entry or range of entries or all the MCAM entries owned by the pcifunc. Each MCAM entry can be associated with a HW match stat entry if the mailbox requester wants to check the hit count for debugging.
Modified adding default unicast DMAC match rule using install flow API. The default unicast DMAC match entry installed by Administrative Function is saved and can be changed later by the mailbox user to fit additional fields, or the default MCAM entry rule action can be used for other flow rules installed later.
Modified rvu_mbox_handler_nix_lf_free mailbox to add a flag to disable or delete the MCAM entries. The MCAM entries are disabled when the interface is brought down and deleted in FLR handler. The disabled MCAM entries will be re-enabled when the interface is brought up again.
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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f1517f6f |
| 14-Nov-2020 |
Stanislaw Kardach <skardach@marvell.com> |
octeontx2-af: Modify default KEX profile to extract TX packet fields
The current default Key Extraction(KEX) profile can only use RX packet fields while generating the MCAM search key. The profile c
octeontx2-af: Modify default KEX profile to extract TX packet fields
The current default Key Extraction(KEX) profile can only use RX packet fields while generating the MCAM search key. The profile can't be used for matching TX packet fields. This patch modifies the default KEX profile to add support for extracting TX packet fields into MCAM search key. Enabled Tx KPU packet parsing by configuring TX PKIND in tx_parse_cfg.
Modified the KEX profile to extract 2 bytes of VLAN TCI from an offset of 2 bytes from LB_PTR. The LB_PTR points to the byte offset where the VLAN header starts. The NPC KPU parser profile has been modified to point LB_PTR to the starting byte offset of VLAN header which points to the tpid field.
Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Revision tags: v5.8.17 |
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a84cdcea |
| 29-Oct-2020 |
Subbaraya Sundeep <sbhatta@marvell.com> |
octeontx2-af: Mbox changes for 98xx
This patch puts together all mailbox changes for 98xx silicon:
Attach -> Modify resource attach mailbox handler to request LFs from a block address out of multip
octeontx2-af: Mbox changes for 98xx
This patch puts together all mailbox changes for 98xx silicon:
Attach -> Modify resource attach mailbox handler to request LFs from a block address out of multiple blocks of same type. If a PF/VF need LFs from two blocks of same type then attach mbox should be called twice.
Example: struct rsrc_attach *attach; .. Allocate memory for message .. attach->cptlfs = 3; /* 3 LFs from CPT0 */ .. Send message .. .. Allocate memory for message .. attach->modify = 1; attach->cpt_blkaddr = BLKADDR_CPT1; attach->cptlfs = 2; /* 2 LFs from CPT1 */ .. Send message ..
Detach -> Update detach mailbox and its handler to detach resources from CPT1 and NIX1 blocks.
MSIX -> Updated the MSIX mailbox and its handler to return MSIX offsets for the new block CPT1.
Free resources -> Update free_rsrc mailbox and its handler to return the free resources count of new blocks NIX1 and CPT1
Links -> Number of CGX,LBK and SDP links may vary between platforms. For example, in 98xx number of CGX and LBK links are more than 96xx. Hence the info about number of links present in hardware is useful for consumers to request link configuration properly. This patch sends this info in nix_lf_alloc_rsp.
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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