#
5ee55577 |
| 12-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: prefix Port MAC Control macros For implicit namespacing and clarity, prefix the common MAC Control Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which dif
net: dsa: mv88e6xxx: prefix Port MAC Control macros For implicit namespacing and clarity, prefix the common MAC Control Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which differ between implementations with a chosen reference model (e.g. MV88E6065_PORT_MAC_CTL_SPEED_200.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
5f83dc93 |
| 12-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: prefix Port Status macros For implicit namespacing and clarity, prefix the common Port Status Register macros with MV88E6XXX_PORT_STS and the ones which differ b
net: dsa: mv88e6xxx: prefix Port Status macros For implicit namespacing and clarity, prefix the common Port Status Register macros with MV88E6XXX_PORT_STS and the ones which differ between implementations with a chosen reference model (e.g. MV88E6352_PORT_STS_EEE.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
cd782656 |
| 08-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: rework jumbo size operation Marvell chips have a Jumbo Mode to set the maximum frame size (MTU). The mv88e6xxx_ops structure is meant to contain generic functio
net: dsa: mv88e6xxx: rework jumbo size operation Marvell chips have a Jumbo Mode to set the maximum frame size (MTU). The mv88e6xxx_ops structure is meant to contain generic functionalities, no driver logic. Change port_jumbo_config to port_set_jumbo_size setting the mode from a given maximum size value. There is no functional changes since we still use 10240 bytes. At the same time, correctly clear all Jumbo Mode bits before writing. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
0898432c |
| 08-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: rework pause limit operation All Marvell chips supporting Pause frames limiting use 1-byte value for input and output. Old chips have both bytes adjacent in
net: dsa: mv88e6xxx: rework pause limit operation All Marvell chips supporting Pause frames limiting use 1-byte value for input and output. Old chips have both bytes adjacent in a 16-bit register. New ones have an indirect table using 8-bit data. The mv88e6xxx library functions (such as in port.c) must not contain driver logic, but only generic helpers. This patch changes the port_pause_config operation for port_pause_limit taking two u8 arguments for input and output limits. There is no functional changes. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f894c29c |
| 08-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: use bridge state values Reuse the BR_STATE_* values to abstract a port STP state value. This provides shorter names and better control over the DSA switch o
net: dsa: mv88e6xxx: use bridge state values Reuse the BR_STATE_* values to abstract a port STP state value. This provides shorter names and better control over the DSA switch operation call. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
31bef4e9 |
| 08-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: add egress mode enumeration As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead of a 16-bit register mask. Reviewed-by: Andrew Lunn <andr
net: dsa: mv88e6xxx: add egress mode enumeration As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead of a 16-bit register mask. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
774439e5 |
| 08-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv888e6xxx: do not use netdev printing The mv888e6xxx driver accesses a port's netdev mostly for printing. This is bad for 2 reasons: DSA and CPU ports do not have a netde
net: dsa: mv888e6xxx: do not use netdev printing The mv888e6xxx driver accesses a port's netdev mostly for printing. This is bad for 2 reasons: DSA and CPU ports do not have a netdev pointer; it doesn't give us a correct picture of why a DSA driver might need to access a port's netdev. Instead simply use dev_* printing functions with chip->dev (or ds->dev depending on the scope, both guaranteed to exist), with a p%d prefix for the target port. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
5461bd41 |
| 05-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: fix 6085 frame mode masking The register bits used for the frame mode were masked with DSA (0x1) instead of the mask value (0x3) in the 6085 implementation of po
net: dsa: mv88e6xxx: fix 6085 frame mode masking The register bits used for the frame mode were masked with DSA (0x1) instead of the mask value (0x3) in the 6085 implementation of port_set_frame_mode. Fix this. Fixes: 56995cbc3540 ("net: dsa: mv88e6xxx: Refactor CPU and DSA port setup") Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4d5f2ba7 |
| 02-Jun-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: rename chip header The mv88e6xxx.h is meant to contains the chip structures and data. Rename it to chip.h, as for other source/header pairs of the driver. A
net: dsa: mv88e6xxx: rename chip header The mv88e6xxx.h is meant to contains the chip structures and data. Rename it to chip.h, as for other source/header pairs of the driver. At the same time, ensure that relative header inclusions are separated by a newline and sorted alphabetically. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8, v4.10.7 |
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#
4333d619 |
| 28-Mar-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: fix copyright holder I do not hold the copyright of the DSA core and drivers source files, since these changes have been written as an initiative of my day job. Fix this.
net: dsa: fix copyright holder I do not hold the copyright of the DSA core and drivers source files, since these changes have been written as an initiative of my day job. Fix this. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.10.6, v4.10.5, v4.10.4, v4.10.3, v4.10.2 |
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#
9dbfb4e1 |
| 11-Mar-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: add port priority override op Add a new operation to disable the DA, SA and VTU priority override. Setting such limit is not likely to be used soon, so provide
net: dsa: mv88e6xxx: add port priority override op Add a new operation to disable the DA, SA and VTU priority override. Setting such limit is not likely to be used soon, so provide a port_disable_pri_override operation directly. This can be changed later for port_set_pri_override when we'll need it. Also remove the now obsolete mv88e6xxx_6320_family helper. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
c8c94891 |
| 11-Mar-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: add port ATU learn limit op Add a new operation to disable the limiting of learnt MAC addresses. Setting such limit is not likely to be used soon, so provide a
net: dsa: mv88e6xxx: add port ATU learn limit op Add a new operation to disable the limiting of learnt MAC addresses. Setting such limit is not likely to be used soon, so provide a port_disable_learn_limit operation directly. This can be changed later for port_set_learn_limit when we'll need it. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
601aeed3 |
| 11-Mar-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: fix port egress flooding mode The Marvell switch ports can be configured to allow or prevent egress of frames with an unknown unicast or multicast destination addres
net: dsa: mv88e6xxx: fix port egress flooding mode The Marvell switch ports can be configured to allow or prevent egress of frames with an unknown unicast or multicast destination address. Some switch chips such as 88E6095 and 88E6185 have two disjoint bits in Port Control Register (0x04) bit 2 "Forward Unknown" (for unicast) and Port Control 2 Register (0x08) bit 6 "Default Forward" (for multicast). Other chips such as 88E6085, 88E6123, 88E6352, and 88E6390 have a 2-bit value in Port Control Register (0x04) bits 3:2 "EgressFloods". The current code does not fully implement the disjoint bits variant and assigns incorrect ones to some chip models. Fix that with two implementation references (6185 and 6352 that I currently have) of a port_set_egress_floods operation (as named in datasheets). Old chips such as 88E6060 don't have egress flooding mode, so don't error out if the operation is not provided. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ea698f4f |
| 11-Mar-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: setup message ports All interconnectable Marvell switch chips have an ATU Learn2All feature which allows newly learnt addresses to be spanned on ports marked as
net: dsa: mv88e6xxx: setup message ports All interconnectable Marvell switch chips have an ATU Learn2All feature which allows newly learnt addresses to be spanned on ports marked as "Message Port". This commit configures the DSA ports as Message Port. Note that this has no effect until the Learn2All feature is enabled. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
4d294af2 |
| 11-Mar-2017 |
Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
net: dsa: mv88e6xxx: add port mask helper Add a mv88e6xxx_port_mask() helper to get the bitmask of ports in a switch chip, that will be used in several features. Signed-off-by:
net: dsa: mv88e6xxx: add port mask helper Add a mv88e6xxx_port_mask() helper to get the bitmask of ports in a switch chip, that will be used in several features. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.10.1, v4.10 |
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#
a23b2961 |
| 04-Feb-2017 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Refactor remaining port setup Move the remaining port configuration code which varies per device into port.c, using ops were necessary. This makes mv88e6xxx_6185
net: dsa: mv88e6xxx: Refactor remaining port setup Move the remaining port configuration code which varies per device into port.c, using ops were necessary. This makes mv88e6xxx_6185_family() and mv88e6xxx_6095_family() unused, so remove them. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
f39908d3 |
| 04-Feb-2017 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Set the CMODE for mv88e6390 ports 9 & 10 Unlike most ports, ports 9 and 10 of the 6390X family have configurable PHY modes. Set the mode as part of adjust_link().
net: dsa: mv88e6xxx: Set the CMODE for mv88e6390 ports 9 & 10 Unlike most ports, ports 9 and 10 of the 6390X family have configurable PHY modes. Set the mode as part of adjust_link(). Ordering is important, because the SERDES interfaces connected to ports 9 and 10 can be split and assigned to other ports. The CMODE has to be correctly set before the SERDES interface on another port can be configured. Such configuration is likely to be performed in port_enable() and port_disabled(), called on slave_open() and slave_close(). The simple case is port 9 and 10 are used for 'CPU' or 'DSA'. In this case, the CMODE is set via a phy-mode in dsa_cpu_dsa_setup(), which is called early in the switch setup. When ports 9 or 10 are used as user ports, and have a fixed-phy, when the fixed fixed-phy is attached, dsa_slave_adjust_link() is called, which results in the adjust_link function being called, setting the cmode. The port_enable() will for other ports will be called much later. When ports 9 or 10 are used as user ports and have a real phy attached which does not use all the available SERDES interface, e.g. a 1Gbps SGMII, there is currently no mechanism in place to set the CMODE of the port from software. It must be hoped the stripping resistors are correct. At the same time, add a function to get the cmode. This will be needed when configuring the SERDES interfaces. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
740117a8 |
| 01-Feb-2017 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Fix typ0 when configuring 2.5Gbps In order to enable 2.5Gbps mode, we need the base speed of 10G, plus the Alt bit setting. Fix a typ0 that used 1Gb base speed.
net: dsa: mv88e6xxx: Fix typ0 when configuring 2.5Gbps In order to enable 2.5Gbps mode, we need the base speed of 10G, plus the Alt bit setting. Fix a typ0 that used 1Gb base speed. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v4.9 |
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#
3ce0e65e |
| 02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Implement mv88e6390 pause control The mv88e6390 has a number flow control registers accessed via the Flow Control register. Use these to set the pause control.
net: dsa: mv88e6xxx: Implement mv88e6390 pause control The mv88e6390 has a number flow control registers accessed via the Flow Control register. Use these to set the pause control. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
b35d322a |
| 02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Refactor pause configuration The mv88e6390 has a different mechanism for configuring pause. Refactor the code into an ops function, and for the moment, don't add
net: dsa: mv88e6xxx: Refactor pause configuration The mv88e6390 has a different mechanism for configuring pause. Refactor the code into an ops function, and for the moment, don't add any mv88e6390 code yet. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ef70b111 |
| 02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Refactor egress rate limiting There are two different rate limiting configurations, depending on the switch generation. Refactor this into ops. Signed-off-b
net: dsa: mv88e6xxx: Refactor egress rate limiting There are two different rate limiting configurations, depending on the switch generation. Refactor this into ops. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
5f436666 |
| 02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Refactor setting of jumbo frames Some switches support jumbo frames. Refactor this code into operations in the ops structure. Signed-off-by: Andrew Lunn <an
net: dsa: mv88e6xxx: Refactor setting of jumbo frames Some switches support jumbo frames. Refactor this code into operations in the ops structure. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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#
56995cbc |
| 02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Refactor CPU and DSA port setup Older chips only support DSA tagging. Newer chips have both DSA and EDSA tagging. Refactor the code by adding port functions for sett
net: dsa: mv88e6xxx: Refactor CPU and DSA port setup Older chips only support DSA tagging. Newer chips have both DSA and EDSA tagging. Refactor the code by adding port functions for setting the frame mode, egress mode, and if to forward unknown frames. This results in the helper mv88e6xxx_6065_family() becoming unused, so remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> v3: Verify mandatory ops for port setup Don't set ether type for DSA port. Signed-off-by: David S. Miller <davem@davemloft.net>
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#
ef0a7318 |
| 02-Dec-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Implement mv88e6390 tag remap The mv88e6390 does not have the two registers to set the frame priority map. Instead it has an indirection registers for setting a
net: dsa: mv88e6xxx: Implement mv88e6390 tag remap The mv88e6390 does not have the two registers to set the frame priority map. Instead it has an indirection registers for setting a number of different priority maps. Refactor the old code into an function, implement the mv88e6390 version, and use an op to call the right one. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: openbmc-4.4-20161121-1, v4.4.33 |
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#
0b6e3d03 |
| 15-Nov-2016 |
Andrew Lunn <andrew@lunn.ch> |
net: dsa: mv88e6xxx: Respect SPEED_UNFORCED, don't set force bit The SPEED_UNFORCED indicates the MAC & PHY should perform auto-negotiation to determine a speed which works. If this is c
net: dsa: mv88e6xxx: Respect SPEED_UNFORCED, don't set force bit The SPEED_UNFORCED indicates the MAC & PHY should perform auto-negotiation to determine a speed which works. If this is called for, don't set the force bit. If it is set, the MAC actually does 10Gbps, why the internal PHYs don't support. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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