Revision tags: v5.10 |
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#
8ffbfe43 |
| 12-Nov-2020 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
mmc: sdhci-msm: detect if tassadar_dll is used by using core version
Detect if tassadar_dll is required by using core version rather than just specifying it in the sdhci_msm_variant_info.
Signed-of
mmc: sdhci-msm: detect if tassadar_dll is used by using core version
Detect if tassadar_dll is required by using core version rather than just specifying it in the sdhci_msm_variant_info.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Reviewed-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/20201112173636.360186-1-dmitry.baryshkov@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3f8920c5 |
| 16-Jul-2021 |
Shaik Sajida Bhanu <sbhanu@codeaurora.org> |
mmc: sdhci-msm: Update the software timeout value for sdhc
[ Upstream commit 67b13f3e221ed81b46a657e2b499bf8b20162476 ]
Whenever SDHC run at clock rate 50MHZ or below, the hardware data timeout val
mmc: sdhci-msm: Update the software timeout value for sdhc
[ Upstream commit 67b13f3e221ed81b46a657e2b499bf8b20162476 ]
Whenever SDHC run at clock rate 50MHZ or below, the hardware data timeout value will be 21.47secs, which is approx. 22secs and we have a current software timeout value as 10secs. We have to set software timeout value more than the hardware data timeout value to avioid seeing the below register dumps.
[ 332.953670] mmc2: Timeout waiting for hardware interrupt. [ 332.959608] mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== [ 332.966450] mmc2: sdhci: Sys addr: 0x00000000 | Version: 0x00007202 [ 332.973256] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001 [ 332.980054] mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000027 [ 332.986864] mmc2: sdhci: Present: 0x01f801f6 | Host ctl: 0x0000001f [ 332.993671] mmc2: sdhci: Power: 0x00000001 | Blk gap: 0x00000000 [ 333.000583] mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x00000007 [ 333.007386] mmc2: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000 [ 333.014182] mmc2: sdhci: Int enab: 0x03ff100b | Sig enab: 0x03ff100b [ 333.020976] mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 [ 333.027771] mmc2: sdhci: Caps: 0x322dc8b2 | Caps_1: 0x0000808f [ 333.034561] mmc2: sdhci: Cmd: 0x0000183a | Max curr: 0x00000000 [ 333.041359] mmc2: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x00000000 [ 333.048157] mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 [ 333.054945] mmc2: sdhci: Host ctl2: 0x00000000 [ 333.059657] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000ffffff218 [ 333.067178] mmc2: sdhci_msm: ----------- VENDOR REGISTER DUMP ----------- [ 333.074343] mmc2: sdhci_msm: DLL sts: 0x00000000 | DLL cfg: 0x6000642c | DLL cfg2: 0x0020a000 [ 333.083417] mmc2: sdhci_msm: DLL cfg3: 0x00000000 | DLL usr ctl: 0x00000000 | DDR cfg: 0x80040873 [ 333.092850] mmc2: sdhci_msm: Vndr func: 0x00008a9c | Vndr func2 : 0xf88218a8 Vndr func3: 0x02626040 [ 333.102371] mmc2: sdhci: ============================================
So, set software timeout value more than hardware timeout value.
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1626435974-14462-1-git-send-email-sbhanu@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8 |
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#
91ca244b |
| 09-Sep-2020 |
Viresh Kumar <viresh.kumar@linaro.org> |
mmc: sdhci-msm: Unconditionally call dev_pm_opp_of_remove_table()
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to find the OPP table with error -ENODEV (i.e. OPP table not pr
mmc: sdhci-msm: Unconditionally call dev_pm_opp_of_remove_table()
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to find the OPP table with error -ENODEV (i.e. OPP table not present for the device). And we can call dev_pm_opp_of_remove_table() unconditionally here.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/890ae5601594fca5de104695a682f4b6efbc631b.1599660554.git.viresh.kumar@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.8.7, v5.8.6, v5.4.62 |
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#
8c98644b |
| 02-Sep-2020 |
Douglas Anderson <dianders@chromium.org> |
mmc: sdhci-msm: Prefer asynchronous probe
Turning on initcall debug on one system showed this: initcall sdhci_msm_driver_init+0x0/0x28 returned 0 after 34782 usecs
The lion's share of this time (
mmc: sdhci-msm: Prefer asynchronous probe
Turning on initcall debug on one system showed this: initcall sdhci_msm_driver_init+0x0/0x28 returned 0 after 34782 usecs
The lion's share of this time (~33 ms) was in mmc_power_up(). This shouldn't be terribly surprising since there are a few calls to delay based on "power_delay_ms" and the default delay there is 10 ms.
Because we haven't specified that we'd prefer asynchronous probe for this driver then we'll wait for this driver to finish before we start probes for more drivers. While 33 ms doesn't sound like tons, every little bit counts.
There should be little problem with turning on asynchronous probe for this driver. It's already possible that previous drivers may have turned on asynchronous probe so we might already have other things (that probed before us) probing at the same time we are anyway. This driver isn't really providing resources (clocks, regulators, etc) that other drivers need to probe and even if it was they should be handling -EPROBE_DEFER.
Let's turn this on and get a bit of boot speed back.
Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200902164303.1.I5e598a25222b4534c0083b61dbfa4e0e76f66171@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
4dac686b |
| 27-Aug-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Enable restore_dll_config flag for sc7180 target
On sc7180 target, issues are observed with HS400 mode due to a hardware limitation. If sdcc clock is dynamically gated and ungated, t
mmc: sdhci-msm: Enable restore_dll_config flag for sc7180 target
On sc7180 target, issues are observed with HS400 mode due to a hardware limitation. If sdcc clock is dynamically gated and ungated, the very next command is failing with command CRC/timeout errors.
To mitigate this issue, DLL phase has to be restored whenever sdcc clock is gated dynamically. The restore_dll_config ensures this. Enabling this flag with this change. And simply re-using the sdm845 target configuration for this flag.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1598541694-15694-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
9d5dcefb |
| 27-Aug-2020 |
Douglas Anderson <dianders@chromium.org> |
mmc: sdhci-msm: Add retries when all tuning phases are found valid
As the comments in this patch say, if we tune and find all phases are valid it's _almost_ as bad as no phases being found valid. P
mmc: sdhci-msm: Add retries when all tuning phases are found valid
As the comments in this patch say, if we tune and find all phases are valid it's _almost_ as bad as no phases being found valid. Probably all phases are not really reliable but we didn't detect where the unreliable place is. That means we'll essentially be guessing and hoping we get a good phase.
This is not just a problem in theory. It was causing real problems on a real board. On that board, most often phase 10 is found as the only invalid phase, though sometimes 10 and 11 are invalid and sometimes just 11. Some percentage of the time, however, all phases are found to be valid. When this happens, the current logic will decide to use phase 11. Since phase 11 is sometimes found to be invalid, this is a bad choice. Sure enough, when phase 11 is picked we often get mmc errors later in boot.
I have seen cases where all phases were found to be valid 3 times in a row, so increase the retry count to 10 just to be extra sure.
Fixes: 415b5a75da43 ("mmc: sdhci-msm: Add platform_execute_tuning implementation") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200827075809.1.If179abf5ecb67c963494db79c3bc4247d987419b@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51 |
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#
b5c833b7 |
| 08-Jul-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Set IO pins in low power state during suspend
Configure SDHC IO pins with low power configuration when the driver is in suspend state.
Signed-off-by: Veerabhadrarao Badiganti <vbadi
mmc: sdhci-msm: Set IO pins in low power state during suspend
Configure SDHC IO pins with low power configuration when the driver is in suspend state.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1594213888-2780-2-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
abf4633a |
| 01-Jul-2020 |
Lee Jones <lee.jones@linaro.org> |
mmc: sdhci-msm: Demote faux kerneldoc header down to basic comment block
__sdhci_msm_set_clock()'s function header is the only one in kerneldoc format. Which seems odd as it's not part of an extern
mmc: sdhci-msm: Demote faux kerneldoc header down to basic comment block
__sdhci_msm_set_clock()'s function header is the only one in kerneldoc format. Which seems odd as it's not part of an external API and isn't referenced anywhere else. Seeing as there has also been no attempt to describe the expected function arguments either, we're going to assume that this is not actually a bona fide kerneldoc use-case.
Fixes the following W=1 kernel build warnings:
drivers/mmc/host/sdhci-msm.c:1595: warning: Function parameter or member 'host' not described in '__sdhci_msm_set_clock' drivers/mmc/host/sdhci-msm.c:1595: warning: Function parameter or member 'clock' not described in '__sdhci_msm_set_clock'
Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20200701124702.908713-14-lee.jones@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
53e888d1 |
| 01-Jul-2020 |
Hulk Robot <hulkci@huawei.com> |
mmc: sdhci-msm: Make function sdhci_msm_dump_vendor_regs() static
Fix sparse build warning:
drivers/mmc/host/sdhci-msm.c:1888:6: warning: symbol 'sdhci_msm_dump_vendor_regs' was not declared. Shou
mmc: sdhci-msm: Make function sdhci_msm_dump_vendor_regs() static
Fix sparse build warning:
drivers/mmc/host/sdhci-msm.c:1888:6: warning: symbol 'sdhci_msm_dump_vendor_regs' was not declared. Should it be static?
Signed-off-by: Hulk Robot <hulkci@huawei.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200702020347.77214-1-weiyongjun1@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.50, v5.7.7, v5.4.49, v5.7.6 |
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#
92a21738 |
| 23-Jun-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Use internal voltage control
On qcom SD host controllers voltage switching be done after the HW is ready for it. The HW informs its readiness through power irq. The voltage switching
mmc: sdhci-msm: Use internal voltage control
On qcom SD host controllers voltage switching be done after the HW is ready for it. The HW informs its readiness through power irq. The voltage switching should happen only then.
Use the internal voltage switching and then control the voltage switching using power irq.
IO-bus supply of eMMC would be kept always-on. So set the load for this supply to configure it in LPM when eMMC is suspend state and in HPM when eMMC is active.
Co-developed-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Co-developed-by: Vijay Viswanath <vviswana@codeaurora.org> Signed-off-by: Vijay Viswanath <vviswana@codeaurora.org> Co-developed-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1592919288-1020-4-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.7.5, v5.4.48, v5.7.4 |
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#
27d8a86a |
| 17-Jun-2020 |
Flavio Suligoi <f.suligoi@asem.it> |
mmc: sdhci-msm: Fix spelling mistake
Fix typo: "trigered" --> "triggered"
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kern
mmc: sdhci-msm: Fix spelling mistake
Fix typo: "trigered" --> "triggered"
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200617151938.30217-1-f.suligoi@asem.it Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.7.3, v5.4.47, v5.4.46, v5.7.2 |
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#
b4fc8278 |
| 09-Jun-2020 |
Pradeep P V K <ppvk@codeaurora.org> |
mmc: sdhci-msm: Add interconnect bandwidth scaling support
Interconnect bandwidth scaling support is now added as a part of OPP. So, make sure interconnect driver is ready before handling interconne
mmc: sdhci-msm: Add interconnect bandwidth scaling support
Interconnect bandwidth scaling support is now added as a part of OPP. So, make sure interconnect driver is ready before handling interconnect scaling.
Signed-off-by: Pradeep P V K <ppvk@codeaurora.org> Reviewed-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1591691846-7578-2-git-send-email-ppvk@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
3ec2d511 |
| 08-Jul-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Override DLL_CONFIG only if the valid value is supplied
During DLL initialization, the DLL_CONFIG register value would be updated with the value supplied from the device-tree.
Overr
mmc: sdhci-msm: Override DLL_CONFIG only if the valid value is supplied
During DLL initialization, the DLL_CONFIG register value would be updated with the value supplied from the device-tree.
Override this register only if a valid value is supplied.
Fixes: 03591160ca19 ("mmc: sdhci-msm: Read and use DLL Config property from device tree file") Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1594213888-2780-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.45, v5.7.1, v5.4.44, v5.7 |
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#
9253d710 |
| 28-May-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Clear tuning done flag while hs400 tuning
Clear tuning_done flag while executing tuning to ensure vendor specific HS400 settings are applied properly when the controller is re-initia
mmc: sdhci-msm: Clear tuning done flag while hs400 tuning
Clear tuning_done flag while executing tuning to ensure vendor specific HS400 settings are applied properly when the controller is re-initialized in HS400 mode.
Without this, re-initialization of the qcom SDHC in HS400 mode fails while resuming the driver from runtime-suspend or system-suspend.
Fixes: ff06ce417828 ("mmc: sdhci-msm: Add HS400 platform support") Cc: stable@vger.kernel.org Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Link: https://lore.kernel.org/r/1590678838-18099-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.43 |
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#
16d18d89 |
| 22-May-2020 |
Sarthak Garg <sartgarg@codeaurora.org> |
mmc: sdhci-msm: dump vendor specific registers during error
Implement dump_vendor_registers host operation to print the vendor specific registers in addition to standard SDHC register during error c
mmc: sdhci-msm: dump vendor specific registers during error
Implement dump_vendor_registers host operation to print the vendor specific registers in addition to standard SDHC register during error conditions.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1590139950-7288-9-git-send-email-sartgarg@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
03591160 |
| 22-May-2020 |
Sarthak Garg <sartgarg@codeaurora.org> |
mmc: sdhci-msm: Read and use DLL Config property from device tree file
Certain platforms require different settings in the SDCC_HC_REG_DLL_CONFIG register. This setting can change from platform to p
mmc: sdhci-msm: Read and use DLL Config property from device tree file
Certain platforms require different settings in the SDCC_HC_REG_DLL_CONFIG register. This setting can change from platform to platform. So the driver should check whether a particular platform require a different setting by reading the DT file and use it.
Also use msm_cm_dll_set_freq only when DLL not supplied.
Signed-off-by: Bao D. Nguyen <nguyenb@codeaurora.org> Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1590139950-7288-7-git-send-email-sartgarg@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
1dfbe3ff |
| 22-May-2020 |
Sarthak Garg <sartgarg@codeaurora.org> |
mmc: sdhci-msm: Update DDR_CONFIG as per device tree file
Certain platforms require different settings in the SDCC_HC_REG_DDR_CONFIG register. This setting can change from platform to platform. So t
mmc: sdhci-msm: Update DDR_CONFIG as per device tree file
Certain platforms require different settings in the SDCC_HC_REG_DDR_CONFIG register. This setting can change from platform to platform. So the driver should check whether a particular platform require a different setting by reading the device tree file and use it.
Signed-off-by: Bao D. Nguyen <nguyenb@codeaurora.org> Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1590139950-7288-6-git-send-email-sartgarg@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
04816e67 |
| 22-May-2020 |
Sarthak Garg <sartgarg@codeaurora.org> |
mmc: sdhci-msm: Update dll_config_3 as per HSR
Update dll_config_3 as per the host clock frequency as specified in the DLL Hardware Reference Guide.
Signed-off-by: Sarthak Garg <sartgarg@codeaurora
mmc: sdhci-msm: Update dll_config_3 as per HSR
Update dll_config_3 as per the host clock frequency as specified in the DLL Hardware Reference Guide.
Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1590139950-7288-5-git-send-email-sartgarg@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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#
5c30f340 |
| 22-May-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: host: sdhci-msm: Configure dll-user-control in dll init sequence
With SDCC v5.1.0, additional setting needed for enabling DLL output. The dll-user-control register need to be configured during
mmc: host: sdhci-msm: Configure dll-user-control in dll init sequence
With SDCC v5.1.0, additional setting needed for enabling DLL output. The dll-user-control register need to be configured during dll initialization for getting proper dll output.
Without this configuration, we don't get the DLL lock status properly. Also update the DLL register settings according to the SDCC Hardware Programming Guide.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1590139950-7288-4-git-send-email-sartgarg@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36 |
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#
c2b613d0 |
| 28-Apr-2020 |
Rajendra Nayak <rnayak@codeaurora.org> |
mmc: sdhci-msm: Fix error handling for dev_pm_opp_of_add_table()
Even though specifying OPP's in device tree is optional, ignoring all errors reported by dev_pm_opp_of_add_table() means we can't dis
mmc: sdhci-msm: Fix error handling for dev_pm_opp_of_add_table()
Even though specifying OPP's in device tree is optional, ignoring all errors reported by dev_pm_opp_of_add_table() means we can't distinguish between a missing OPP table and a wrong/buggy OPP table. While missing OPP table (dev_pm_opp_of_add_table() returns a -ENODEV in such case) can be ignored, a wrong/buggy OPP table in device tree should make the driver error out.
while we fix that, lets also fix the variable names for opp/opp_table to avoid confusion and name them opp_table/has_opp_table instead.
Suggested-by: Matthias Kaehlcke <matthias@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1588080785-6812-10-git-send-email-rnayak@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.35, v5.4.34 |
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#
0472f8d3 |
| 17-Apr-2020 |
Rajendra Nayak <rnayak@codeaurora.org> |
mmc: sdhci-msm: Use OPP API to set clk/perf state
On some qualcomm SoCs we need to vote on a performance state of a power domain depending on the clock rates. Hence move to using OPP api to set the
mmc: sdhci-msm: Use OPP API to set clk/perf state
On some qualcomm SoCs we need to vote on a performance state of a power domain depending on the clock rates. Hence move to using OPP api to set the clock rate and performance state specified in the OPP table. On platforms without an OPP table, dev_pm_opp_set_rate() is eqvivalent to clk_set_rate()
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1587132279-27659-10-git-send-email-rnayak@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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946932d9 |
| 20-Apr-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Enable ADMA length mismatch error interrupt
ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls ADMA length mismatch error interrupt. Enable it by default.
And update all
mmc: sdhci-msm: Enable ADMA length mismatch error interrupt
ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls ADMA length mismatch error interrupt. Enable it by default.
And update all bit shift defines with BIT macro.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1587363626-20413-4-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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d863cb03 |
| 20-Apr-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk
sdhci-msm can support auto cmd12. So enable SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@
mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk
sdhci-msm can support auto cmd12. So enable SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1587363626-20413-3-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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9d8cb586 |
| 20-Apr-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Enable host capabilities pertains to R1b response
MSM sd host controller is capable of HW busy detection of device busy signaling over DAT0 line. And it requires the R1B response for
mmc: sdhci-msm: Enable host capabilities pertains to R1b response
MSM sd host controller is capable of HW busy detection of device busy signaling over DAT0 line. And it requires the R1B response for commands that have this response associated with them.
So set the below two host capabilities for qcom SDHC. - MMC_CAP_WAIT_WHILE_BUSY - MMC_CAP_NEED_RSP_BUSY
Recent development of the mmc core in regards to this, revealed this as being a potential bug, hence the stable tag.
Cc: <stable@vger.kernel.org> # v4.19+ Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1587363626-20413-2-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Revision tags: v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25 |
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5cf583f1 |
| 06-Mar-2020 |
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> |
mmc: sdhci-msm: Deactivate CQE during SDHC reset
When SDHC gets reset (E.g. in runtime suspend path), CQE also gets reset and goes to disable state. But s/w state still points it as CQE is in enable
mmc: sdhci-msm: Deactivate CQE during SDHC reset
When SDHC gets reset (E.g. in runtime suspend path), CQE also gets reset and goes to disable state. But s/w state still points it as CQE is in enabled state. Since s/w and h/w states goes out of sync, it results in s/w request timeout for subsequent CQE requests.
To synchronize CQE s/w and h/w state during SDHC reset, explicitly deactivate CQE just before SDHC reset.
Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1583503724-13943-3-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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