| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
|
Revision tags: v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15 |
|
| #
bce724fa |
| 09-Feb-2021 |
Joel Stanley <joel@jms.id.au> |
drm/aspeed: Use dt matching for default register values
There are minor differences in the values for the threshold value and
the scan line size between families of ASPEED SoC. Additionally the SCU
drm/aspeed: Use dt matching for default register values
There are minor differences in the values for the threshold value and
the scan line size between families of ASPEED SoC. Additionally the SCU
registers for the output control and scratch registers differ between
families.
This adds device tree matching to parameterise these values, allowing us
to add support for the AST2400 now, and in the future the AST2600.
Reviewed-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20210209123734.130483-3-joel@jms.id.au
show more ...
|
|
Revision tags: v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22 |
|
| #
c76eb355 |
| 22-Feb-2020 |
Ondrej Jirman <megous@megous.com> |
drm: aspeed: Fix GENMASK misuse
Arguments to GENMASK should be msb >= lsb.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley
drm: aspeed: Fix GENMASK misuse
Arguments to GENMASK should be msb >= lsb.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20200222235152.242816-1-megous@megous.com
show more ...
|
| #
2dbb5aeb |
| 09-Feb-2021 |
Joel Stanley <joel@jms.id.au> |
drm/aspeed: Use dt matching for default register values
There are minor differences in the values for the threshold value and
the scan line size between families of ASPEED SoC. Additionally the SCU
drm/aspeed: Use dt matching for default register values
There are minor differences in the values for the threshold value and
the scan line size between families of ASPEED SoC. Additionally the SCU
registers for the output control and scratch registers differ between
families.
This adds device tree matching to parameterise these values, allowing us
to add support for the AST2400 now, and in the future the AST2600.
Reviewed-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20210209123734.130483-3-joel@jms.id.au
(cherry picked from commit bce724fa58e67d24fe9eddb40ebb665fbe4bd7e8)
Signed-off-by: Joel Stanley <joel@jms.id.au>
show more ...
|
| #
cd829454 |
| 15-Apr-2020 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/aspeed: Use devm_drm_dev_alloc
As usual, we can drop the drm_dev_put() and need to embed the
drm_device. Since it's so few, also go right ahead and leave
drm_device->dev_private set to NULL, so
drm/aspeed: Use devm_drm_dev_alloc
As usual, we can drop the drm_dev_put() and need to embed the
drm_device. Since it's so few, also go right ahead and leave
drm_device->dev_private set to NULL, so that we always use the
container_of() upcast, which is faster anyway.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: linux-aspeed@lists.ozlabs.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200415074034.175360-56-daniel.vetter@ffwll.ch
show more ...
|
| #
e95d2f40 |
| 15-Apr-2020 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
drm/aspeed: Drop aspeed_gfx->fbdev
No longer used since the conversion to generic fbdev.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Joel St
drm/aspeed: Drop aspeed_gfx->fbdev
No longer used since the conversion to generic fbdev.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: linux-aspeed@lists.ozlabs.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://patchwork.freedesktop.org/patch/msgid/20200415074034.175360-55-daniel.vetter@ffwll.ch
show more ...
|
|
Revision tags: v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10, v5.0.9, v5.0.8, v5.0.7, v5.0.6 |
|
| #
4f2a8f58 |
| 02-Apr-2019 |
Joel Stanley <joel@jms.id.au> |
drm: Add ASPEED GFX driver
This driver is for the ASPEED BMC SoC's GFX display hardware. This
driver runs on the ARM based BMC systems, unlike the ast driver which
runs on a host CPU and is is for a
drm: Add ASPEED GFX driver
This driver is for the ASPEED BMC SoC's GFX display hardware. This
driver runs on the ARM based BMC systems, unlike the ast driver which
runs on a host CPU and is is for a PCI graphics device.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Noralf Trønnes <noralf@tronnes.org>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190403001909.31637-3-joel@jms.id.au
show more ...
|