| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|
| #
d525d3d0 |
| 01-Mar-2022 |
Tommy Haung <tommy_huang@aspeedtech.com> |
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel
drm/aspeed: Update INTR_STS handling
Add interrupt clear register define for further chip support.
OpenBMC-Staging-Count: 1
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
show more ...
|