|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
1e3b8874 |
| 27-Mar-2024 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state result
drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11
commit 31729e8c21ecfd671458e02b6511eb68c2225113 upstream.
While doing multiple S4 stress tests, GC/RLC/PMFW get into
an invalid state resulting into hard hangs.
Adding a GFX reset as workaround just before sending the
MP1_UNLOAD message avoids this failure.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Mario Limonciello <superm1@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
show more ...
|
|
Revision tags: v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45 |
|
| #
9366c2e8 |
| 10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <ale
drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
62942567 |
| 10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Fix SMU 13.0.4/13.0.11 GPU metrics average power
The average power for the GPU metrics sysfs file contains the input
power not the average power. The member that is set is called average
p
drm/amd: Fix SMU 13.0.4/13.0.11 GPU metrics average power
The average power for the GPU metrics sysfs file contains the input
power not the average power. The member that is set is called average
power though, so correct it to the right value.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
47f1724d |
| 10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`
Some GPUs have been overloading average power values and input power
values. To disambiguate these, introduce a new
`AMDGPU_PP_SENSOR_GPU_INPUT_
drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`
Some GPUs have been overloading average power values and input power
values. To disambiguate these, introduce a new
`AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input
power update to use this instead of average power.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2746
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33 |
|
| #
55682a89 |
| 05-Jun-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: enable more Pstates profile levels for SMU v13.0.4
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profi
drm/amd/pm: enable more Pstates profile levels for SMU v13.0.4
This patch enables following UMD stable Pstates profile
levels for power_dpm_force_performance_level interface.
- profile_peak
- profile_min_mclk
- profile_min_sclk
- profile_standard
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.1.32 |
|
| #
2d0ee64e |
| 02-Jun-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: enable vclk and dclk Pstates for SMU v13.0.4
Add the ability to control the vclk and dclk frequency by
power_dpm_force_performance_level interface.
Signed-off-by: Tim Huang <Tim.Huang@a
drm/amd/pm: enable vclk and dclk Pstates for SMU v13.0.4
Add the ability to control the vclk and dclk frequency by
power_dpm_force_performance_level interface.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
27d196c4 |
| 06-Jun-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fix vclk setting failed for SMU v13.0.4
PMFW use the left-shifted 16 bits argument to set the VCLK
DPM frequency for SMU v13.0.4.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by:
drm/amd/pm: fix vclk setting failed for SMU v13.0.4
PMFW use the left-shifted 16 bits argument to set the VCLK
DPM frequency for SMU v13.0.4.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.1.31, v6.1.30 |
|
| #
665d49c2 |
| 20-May-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: reverse mclk and fclk clocks levels for SMU v13.0.4
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk.
On dGPUs and older APUs we expose the levels from lo
drm/amd/pm: reverse mclk and fclk clocks levels for SMU v13.0.4
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk.
On dGPUs and older APUs we expose the levels from lowest clocks
to highest clocks. But for some APUs, the clocks levels that from
the DFPstateTable are given the reversed orders by PMFW. Like the
memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools
and software that talks to the driver then has to know different ways
to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the
driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13 |
|
| #
9661bf68 |
| 21-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Keep interface version in PMFW header
Use the interface version directly from PMFW interface header file rather
than keeping another definition in common smu13 file.
Signed-off-by: Lijo
drm/amd/pm: Keep interface version in PMFW header
Use the interface version directly from PMFW interface header file rather
than keeping another definition in common smu13 file.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
6a07826f |
| 20-May-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: reverse mclk and fclk clocks levels for SMU v13.0.4
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk.
On dGPUs and older APUs we expose the levels from lo
drm/amd/pm: reverse mclk and fclk clocks levels for SMU v13.0.4
This patch reverses the DPM clocks levels output of pp_dpm_mclk
and pp_dpm_fclk.
On dGPUs and older APUs we expose the levels from lowest clocks
to highest clocks. But for some APUs, the clocks levels that from
the DFPstateTable are given the reversed orders by PMFW. Like the
memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools
and software that talks to the driver then has to know different ways
to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the
driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
show more ...
|
|
Revision tags: v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4 |
|
| #
069a5af9 |
| 23-Oct-2022 |
Tim Huang <tim.huang@amd.com> |
drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4
The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use
the different mailbox register offset. So use the specif
drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4
The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use
the different mailbox register offset. So use the specific mailbox
registers offset for v13.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59 |
|
| #
5afb7652 |
| 03-Aug-2022 |
Zhen Ni <nizhen@uniontech.com> |
drm/amd/pm: Fix a potential gpu_metrics_table memory leak
Memory is allocated for gpu_metrics_table in
smu_v13_0_4_init_smc_tables(), but not freed in
smu_v13_0_4_fini_smc_tables(). This may cause m
drm/amd/pm: Fix a potential gpu_metrics_table memory leak
Memory is allocated for gpu_metrics_table in
smu_v13_0_4_init_smc_tables(), but not freed in
smu_v13_0_4_fini_smc_tables(). This may cause memory leaks, fix it.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Zhen Ni <nizhen@uniontech.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
| #
1ff77bea |
| 05-Aug-2022 |
Tim Huang <tim.huang@amd.com> |
drm/amdgpu/pm: remove EnableGfxOff message for SMU IP v13.0.4
The EnableGfxOff message is dropped from the new PMFW ppsmc interface.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan
drm/amdgpu/pm: remove EnableGfxOff message for SMU IP v13.0.4
The EnableGfxOff message is dropped from the new PMFW ppsmc interface.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46 |
|
| #
526e6ca5 |
| 06-Jun-2022 |
Tim Huang <tim.huang@amd.com> |
drm/amdgpu/pm: remove the repeated EnableGfxImu message sending
The EnableGfxImu message will be issued in the set_gfx_power_up_by_imu.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yif
drm/amdgpu/pm: remove the repeated EnableGfxImu message sending
The EnableGfxImu message will be issued in the set_gfx_power_up_by_imu.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
|
Revision tags: v5.15.45, v5.15.44 |
|
| #
da1db031 |
| 26-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for
accessing the SMU mailboxes without needing a lot of
per asic logic in the common
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for
accessing the SMU mailboxes without needing a lot of
per asic logic in the common code.
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.43, v5.15.42, v5.18 |
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| #
7101ab97 |
| 18-May-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function
GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Hua
drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function
GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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| #
2c270d3e |
| 18-May-2022 |
Dan Carpenter <dan.carpenter@oracle.com> |
drm/amdgpu/pm: smu_v13_0_4: delete duplicate condition
There is no need to check if "clock_ranges' is non-NULL. It is checked
already on the line before.
Signed-off-by: Dan Carpenter <dan.carpente
drm/amdgpu/pm: smu_v13_0_4: delete duplicate condition
There is no need to check if "clock_ranges' is non-NULL. It is checked
already on the line before.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38 |
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| #
55c89494 |
| 06-May-2022 |
Tim Huang <tim.huang@amd.com> |
drm/amdgpu/pm: add swsmu ppt implementation for SMU IP v13.0.4
Add swsmu ppt files for SMU IP v13.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed
drm/amdgpu/pm: add swsmu ppt implementation for SMU IP v13.0.4
Add swsmu ppt files for SMU IP v13.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
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