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29877868 |
| 04-Mar-2021 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: fix dml prefetch validation [ Upstream commit 8ee0fea4baf90e43efe2275de208a7809f9985bc ] Incorrect variable used, missing initialization during validation.
drm/amd/display: fix dml prefetch validation [ Upstream commit 8ee0fea4baf90e43efe2275de208a7809f9985bc ] Incorrect variable used, missing initialization during validation. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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989a0f67 |
| 11-Jan-2021 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
Revert "drm/amd/display: Fixed Intermittent blue screen on OLED panel" commit 4eec66c014e9a406d8d453de958f6791d05427e4 upstream. commit a861736dae64 ("drm/amd/display: Fixed Intermi
Revert "drm/amd/display: Fixed Intermittent blue screen on OLED panel" commit 4eec66c014e9a406d8d453de958f6791d05427e4 upstream. commit a861736dae64 ("drm/amd/display: Fixed Intermittent blue screen on OLED panel") causes power regression for many users. It seems that this change causes the MCLK to get forced high; this creates a regression for many users since their devices were not able to drop to a low state after this change. For this reason, this reverts commit a861736dae644a0d7abbca0c638ae6aad28feeb8. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1407 Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Naveed Ashfaq <Naveed.Ashfaq@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Roman Li <roman.li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59 |
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#
a861736d |
| 14-Aug-2020 |
Naveed Ashfaq <Naveed.Ashfaq@amd.com> |
drm/amd/display: Fixed Intermittent blue screen on OLED panel [why] Changing to smaller modes on OLED panel caused a blue screen crash as driver reported dram change during vactive w
drm/amd/display: Fixed Intermittent blue screen on OLED panel [why] Changing to smaller modes on OLED panel caused a blue screen crash as driver reported dram change during vactive when it shouldn't [how] Added an extra condition to prevent incorrect dram change timing Signed-off-by: Naveed Ashfaq <Naveed.Ashfaq@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35 |
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#
f00889dc |
| 21-Apr-2020 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: Allow PState switch in VBLANK one display VACTIVE [Why] For certain display configurations we want to allow PSTATE switch when one display can switch in VACTIVE and
drm/amd/display: Allow PState switch in VBLANK one display VACTIVE [Why] For certain display configurations we want to allow PSTATE switch when one display can switch in VACTIVE and the other display can switch in VBLANK [How] Add extra condition to dcn2 pstate support check Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.34, v5.4.33, v5.4.32, v5.4.31 |
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2fdcc916 |
| 05-Apr-2020 |
Jaehyun Chung <jaehyun.chung@amd.com> |
drm/amd/display: Update DRAM watermark before checking to update TTU [Why] In most cases, DRAM watermark is large enough that the result of the condition to increase TTU doesn't chan
drm/amd/display: Update DRAM watermark before checking to update TTU [Why] In most cases, DRAM watermark is large enough that the result of the condition to increase TTU doesn't change after DRAM watermark is increased. However, there is are cases where the condition fails and becomes true after DRAM watermark is increased. This results in minTTU < DRAM watermarks which leads to PSR hang since p-state is requested but not allowed. [How] Check whether to update TTU after DRAM watermark is updated. Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20 |
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a18463ef |
| 13-Feb-2020 |
Alvin Lee <alvin.lee2@amd.com> |
drm/amd/display: Update TTU properly [Why] We need to update TTU properly if DRAMClockChangeWatermark changes. If TTU < DRAMClockChangeWatermark, we pstate won't be allowed and we wi
drm/amd/display: Update TTU properly [Why] We need to update TTU properly if DRAMClockChangeWatermark changes. If TTU < DRAMClockChangeWatermark, we pstate won't be allowed and we will hang in some PSR cases. [How] Update TTU if DramClockChangeWatermark value increases (only if TTU was dependent on the watermark value on the DRAMClockChangeWatermark value in the first place). Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12 |
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#
d4786672 |
| 13-Jan-2020 |
Wenjing Liu <Wenjing.Liu@amd.com> |
drm/amd/display: use odm combine for YCbCr420 timing with h_active greater than 4096 [why] FMT has limitation to support YCbCr420 with h_active greater than 4096. [how] Use
drm/amd/display: use odm combine for YCbCr420 timing with h_active greater than 4096 [why] FMT has limitation to support YCbCr420 with h_active greater than 4096. [how] Use odm combine to overcome the limitation. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4 |
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51f2af1d |
| 16-Dec-2019 |
Charlene Liu <charlene.liu@amd.com> |
drm/amd/display: rename _lvp to l_vp Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.
drm/amd/display: rename _lvp to l_vp Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9 |
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#
5fc11598 |
| 30-Oct-2019 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: expand dml structs Add more fields to support upcoming dml versions Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei
drm/amd/display: expand dml structs Add more fields to support upcoming dml versions Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ad4e140e |
| 01-Nov-2019 |
Joshua Aberback <joshua.aberback@amd.com> |
drm/amd/display: Adjust DML workaround threshold [Why] There is a case where the margin is between 50 and 60, but applying the workaround causes a hang. By increasing the threshold,
drm/amd/display: Adjust DML workaround threshold [Why] There is a case where the margin is between 50 and 60, but applying the workaround causes a hang. By increasing the threshold, we are blocking more cases from switching p-state during active, but those cases will fall back to switching during blank, which is fine. [How] - increase required margin from 50 to 60 Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
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5622b2d6 |
| 01-Oct-2019 |
David Galiffi <David.Galiffi@amd.com> |
drm/amd/display: Create debug option to disable v.active clock change policy. [WHY] It has been a useful option in debugging GFXOFF and P.State Change issues. May be required as for
drm/amd/display: Create debug option to disable v.active clock change policy. [WHY] It has been a useful option in debugging GFXOFF and P.State Change issues. May be required as for platform specific workaround. [HOW] Create option in enum dc_debug_options, "disable_vactive_clock_change". When it is set, dm_dram_clock_change_vactive, will translate into p_state_change_support: false. Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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47f36564 |
| 12-Oct-2019 |
David Galiffi <David.Galiffi@amd.com> |
drm/amd/display: Fix assert observed when performing dummy p-state check [WHY] V.Active dram clock change workaround need a small modification for DMLv2 to ensure that the dummy p-st
drm/amd/display: Fix assert observed when performing dummy p-state check [WHY] V.Active dram clock change workaround need a small modification for DMLv2 to ensure that the dummy p-state check doesn't fail. Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6fcca317 |
| 11-Oct-2019 |
Joshua Aberback <joshua.aberback@amd.com> |
drm/amd/display: Apply vactive dram clock change workaround to dcn2 DMLv2 [Why] This workaround was put in dcn2 DMLv1, and now we need it in DMLv2. Signed-off-by: Joshua Aberbac
drm/amd/display: Apply vactive dram clock change workaround to dcn2 DMLv2 [Why] This workaround was put in dcn2 DMLv1, and now we need it in DMLv2. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12 |
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#
c84ad0d6 |
| 30-Aug-2019 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: update odm mode validation to be in line with policy Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc supp
drm/amd/display: update odm mode validation to be in line with policy Previously 8k30 worked with dsc and odm combine due to a workaround that ran the formula a second time with dsc support enable should dsc validation fail. This worked when clocks were low enough for formula to enable odm to lower voltage, however now broke due to increased clocks. This change updates the ODM combine policy within the formula to properly reflect our current policy within DC, only enabling ODM when we have to, as well as adding a check for viewport width when dsc is enabled. As a side effect the redundant call to dml when odm is required is now unnecessary. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.11, v5.2.10, v5.2.9, v5.2.8 |
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#
b1a47f53 |
| 07-Aug-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: fix DML not calculating delivery time [why] Calculating DCFCLK DS time requires calculating delivery time for luma/chroma, but this value is not calculated in DM
drm/amd/display: fix DML not calculating delivery time [why] Calculating DCFCLK DS time requires calculating delivery time for luma/chroma, but this value is not calculated in DMLv2, it was inadvertently removed when porting DMLv2 [how] Add the calculation back Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1 |
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#
057fc695 |
| 08-Jul-2019 |
Jun Lei <Jun.Lei@amd.com> |
drm/amd/display: support "dummy pstate" [why] Existing support in DC for pstate only accounts for a single latency. This is sufficient when the variance of latency is small, or that
drm/amd/display: support "dummy pstate" [why] Existing support in DC for pstate only accounts for a single latency. This is sufficient when the variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality. Newer ASICs violate both existing assumptions. PState support is mandatory of correct ASIC functionality, but not all latencies have to be supported. Existing code supports a "full p state" which allows memory clock to change, but is hard for DCN to support (as it requires very large buffers). New code will now fall back to a "dummy p state" support when "full p state" cannot be support. This easy p state support should always be allowed. [how] Define a new latency in socBB. Add fallback logic to support it. Note DML is also updated to ensure that fallback will always work. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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