Revision tags: v4.13.16, v4.14 |
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c1fe75c9 |
| 10-Nov-2017 |
Piotr Redlewski <predlewski@gmail.com> |
drm/amd/amdgpu: fix UVD mc offsets
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc cont
drm/amd/amdgpu: fix UVD mc offsets
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end.
Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end.
v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Piotr Redlewski <predlewski@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9953b72f |
| 25-Oct-2017 |
pding <Pixel.Ding@amd.com> |
drm/amdgpu: change redundant init logs to debug level
When this VF stays in exclusive mode for long, other VFs will be impacted.
The redundant messages causes exclusive mode timeout when they're re
drm/amdgpu: change redundant init logs to debug level
When this VF stays in exclusive mode for long, other VFs will be impacted.
The redundant messages causes exclusive mode timeout when they're redirected. That is a normal use case for cloud service to redirect guest log to virtual serial port.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: pding <Pixel.Ding@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.13.5, v4.13, v4.12, v4.10.17, v4.10.16, v4.10.15, v4.10.14, v4.10.13, v4.10.12, v4.10.11, v4.10.10, v4.10.9, v4.10.8 |
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50237287 |
| 30-Mar-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: various cleanups for uvd/vce.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v4.10.7, v4.10.6, v4.10.5, v4.10.4, v4.10.3, v4.10.2, v4.10.1, v4.10, v4.9, openbmc-4.4-20161121-1, v4.4.33, v4.4.32, v4.4.31, v4.4.30, v4.4.29, v4.4.28, v4.4.27, v4.7.10, openbmc-4.4-20161021-1, v4.7.9, v4.4.26, v4.7.8, v4.4.25, v4.4.24, v4.7.7, v4.8, v4.4.23, v4.7.6, v4.7.5, v4.4.22, v4.4.21, v4.7.4, v4.7.3, v4.4.20, v4.7.2, v4.4.19, openbmc-4.4-20160819-1, v4.7.1, v4.4.18, v4.4.17, openbmc-4.4-20160804-1, v4.4.16, v4.7, openbmc-4.4-20160722-1, openbmc-20160722-1, openbmc-20160713-1, v4.4.15, v4.6.4, v4.6.3, v4.4.14, v4.6.2, v4.4.13, openbmc-20160606-1, v4.6.1, v4.4.12, openbmc-20160521-1, v4.4.11, openbmc-20160518-1, v4.6, v4.4.10, openbmc-20160511-1, openbmc-20160505-1, v4.4.9, v4.4.8, v4.4.7 |
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d766e6a3 |
| 29-Mar-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: switch ih handling to two levels (v3)
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP
v2: integrated Christian's comments. v3:
drm/amdgpu: switch ih handling to two levels (v3)
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP
v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: openbmc-20160329-2, openbmc-20160329-1, openbmc-20160321-1, v4.4.6, v4.5 |
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536fbf94 |
| 11-Mar-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: change wptr to 64 bits (v2)
Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore.
v2: integrate Christian's comments.
Si
drm/amdgpu: change wptr to 64 bits (v2)
Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore.
v2: integrate Christian's comments.
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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254cd2e0 |
| 08-Feb-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: read hw register to check pg status.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e3e672e6 |
| 20-Jan-2017 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: refine uvd5.0/6.0 code.
1. delete redundant cg pg mask check. pg mask use to ctrl power on/down uvd. not start/stop uvd. cg mask will be check when enable mgcg. 2. no need to st
drm/amdgpu: refine uvd5.0/6.0 code.
1. delete redundant cg pg mask check. pg mask use to ctrl power on/down uvd. not start/stop uvd. cg mask will be check when enable mgcg. 2. no need to start uvd when initializ. when ring test/ib test/encode, uvd was enabled. when uvd idle, uvd was stopped. 3. chang cg pg sequence in powerplay.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c8781f56 |
| 05-Jan-2017 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: add get clockgating_state method for uvd v5&v6
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander
drm/amdgpu: add get clockgating_state method for uvd v5&v6
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d6df71e1 |
| 21-Dec-2016 |
Yintian Tao <yttao@amd.com> |
drm/amdgpu: remove static integer for uvd pp state
At two gpu core condition, static integer will cause that second gpu core uvd state setting will be directly skipped due to the first one setting
drm/amdgpu: remove static integer for uvd pp state
At two gpu core condition, static integer will cause that second gpu core uvd state setting will be directly skipped due to the first one setting
Signed-off-by: Yintian Tao <yttao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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3c3a7e61 |
| 23-Nov-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: fix bug mclk can't change on Polaris
the root cause is we gate the clock to uvd vcpu. mclk's change should need the response from uvd if it is power on.
Signed-off-by: Rex Zhu <Rex.Zhu@
drm/amdgpu: fix bug mclk can't change on Polaris
the root cause is we gate the clock to uvd vcpu. mclk's change should need the response from uvd if it is power on.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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809a6a62 |
| 08-Nov-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: refine uvd 5.0 clock gate feature.
1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex De
drm/amdgpu: refine uvd 5.0 clock gate feature.
1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0401eb40 |
| 07-Nov-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.co
drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4be5097c |
| 26-Oct-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: enable uvd bypass mode for CI/VI.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Sign
drm/amdgpu: enable uvd bypass mode for CI/VI.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a1255107 |
| 13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework IP block registration (v2)
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also s
drm/amdgpu: rework IP block registration (v2)
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure.
v2: split out spelling fix into a separate patch add a function to add IPs to the list
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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79887142 |
| 05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move align_mask and nop into ring funcs as well (v2)
They are constant as well.
v2: update uvd and vce phys ring structures as well
Signed-off-by: Christian König <christian.koenig@amd
drm/amdgpu: move align_mask and nop into ring funcs as well (v2)
They are constant as well.
v2: update uvd and vce phys ring structures as well
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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21cd942e |
| 05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move the ring type into the funcs structure (v2)
It's constant, so it doesn't make to much sense to keep it with the variable data.
v2: update vce and uvd phys mode ring structures as w
drm/amdgpu: move the ring type into the funcs structure (v2)
It's constant, so it doesn't make to much sense to keep it with the variable data.
v2: update vce and uvd phys mode ring structures as well
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e12f3d7a |
| 05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move IB and frame size directly into the engine description
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc.
Signed-off
drm/amdgpu: move IB and frame size directly into the engine description
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cdbbb784 |
| 16-Sep-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/uvd5: add ring callbacks for ib and dma frame size
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c8b4f288 |
| 23-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: switch UVD code to use UVD_NO_OP for padding
Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter.
Reviewed-by: Christian König <christian
drm/amdgpu: switch UVD code to use UVD_NO_OP for padding
Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8de190c9 |
| 05-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move UVD IB test into common code v2
Since we now raise the clocks from begin_use() we don't need a separate function for each hw generation any more.
v2: remove unintentional lowering
drm/amdgpu: move UVD IB test into common code v2
Since we now raise the clocks from begin_use() we don't need a separate function for each hw generation any more.
v2: remove unintentional lowering of the UVD clocks, fix typos for CIK hw.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c4120d55 |
| 20-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use begin/end_use for UVD power/clock gating
This fixes turning power and clock on when it is actually needed.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edw
drm/amdgpu: use begin/end_use for UVD power/clock gating
This fixes turning power and clock on when it is actually needed.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d5b4e25d |
| 22-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: implement HDP functions for UVD v2
Flush and invalidate the HDP caches.
v2: fix typo in comment
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <ale
drm/amdgpu: implement HDP functions for UVD v2
Flush and invalidate the HDP caches.
v2: fix typo in comment
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d88bf583 |
| 06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move VM fields into job
They are the same for all IBs.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ale
drm/amdgpu: move VM fields into job
They are the same for all IBs.
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f153d286 |
| 06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move context switch handling into common code v2
It was a source of bugs to repeat that in each IP version.
v2: rename parameter
Signed-off-by: Christian König <christian.koenig@amd.co
drm/amdgpu: move context switch handling into common code v2
It was a source of bugs to repeat that in each IP version.
v2: rename parameter
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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88a907d6 |
| 04-May-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add name field to amd_ip_funcs (v2)
Add name that we can print out in kernel messages to aid in debugging.
v2: drop DAL changes for upstream
Signed-off-by: Tom St Denis <tom.stdeni
drm/amd/amdgpu: Add name field to amd_ip_funcs (v2)
Add name that we can print out in kernel messages to aid in debugging.
v2: drop DAL changes for upstream
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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