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3c3a7e61 |
| 23-Nov-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: fix bug mclk can't change on Polaris the root cause is we gate the clock to uvd vcpu. mclk's change should need the response from uvd if it is power on. Signed-o
drm/amdgpu: fix bug mclk can't change on Polaris the root cause is we gate the clock to uvd vcpu. mclk's change should need the response from uvd if it is power on. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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809a6a62 |
| 08-Nov-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: refine uvd 5.0 clock gate feature. 1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Signed-off-by: Rex Zhu <Rex.Zhu@amd.c
drm/amdgpu: refine uvd 5.0 clock gate feature. 1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0401eb40 |
| 07-Nov-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexande
drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4be5097c |
| 26-Oct-2016 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: enable uvd bypass mode for CI/VI. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deuch
drm/amdgpu: enable uvd bypass mode for CI/VI. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a1255107 |
| 13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework IP block registration (v2) This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tabl
drm/amdgpu: rework IP block registration (v2) This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
79887142 |
| 05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move align_mask and nop into ring funcs as well (v2) They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by: Christian Kön
drm/amdgpu: move align_mask and nop into ring funcs as well (v2) They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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21cd942e |
| 05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move the ring type into the funcs structure (v2) It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode
drm/amdgpu: move the ring type into the funcs structure (v2) It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e12f3d7a |
| 05-Oct-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move IB and frame size directly into the engine description I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc.
drm/amdgpu: move IB and frame size directly into the engine description I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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cdbbb784 |
| 16-Sep-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/uvd5: add ring callbacks for ib and dma frame size Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c8b4f288 |
| 23-Aug-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: switch UVD code to use UVD_NO_OP for padding Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter. Reviewed-by: Christ
drm/amdgpu: switch UVD code to use UVD_NO_OP for padding Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8de190c9 |
| 05-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move UVD IB test into common code v2 Since we now raise the clocks from begin_use() we don't need a separate function for each hw generation any more. v2: remove uni
drm/amdgpu: move UVD IB test into common code v2 Since we now raise the clocks from begin_use() we don't need a separate function for each hw generation any more. v2: remove unintentional lowering of the UVD clocks, fix typos for CIK hw. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c4120d55 |
| 20-Jul-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use begin/end_use for UVD power/clock gating This fixes turning power and clock on when it is actually needed. Signed-off-by: Christian König <christian.koenig@amd.com>
drm/amdgpu: use begin/end_use for UVD power/clock gating This fixes turning power and clock on when it is actually needed. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d5b4e25d |
| 22-Jun-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: implement HDP functions for UVD v2 Flush and invalidate the HDP caches. v2: fix typo in comment Signed-off-by: Christian König <christian.koenig@amd.com> Re
drm/amdgpu: implement HDP functions for UVD v2 Flush and invalidate the HDP caches. v2: fix typo in comment Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d88bf583 |
| 06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move VM fields into job They are the same for all IBs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com
drm/amdgpu: move VM fields into job They are the same for all IBs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f153d286 |
| 06-May-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: move context switch handling into common code v2 It was a source of bugs to repeat that in each IP version. v2: rename parameter Signed-off-by: Christian König
drm/amdgpu: move context switch handling into common code v2 It was a source of bugs to repeat that in each IP version. v2: rename parameter Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
88a907d6 |
| 04-May-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add name field to amd_ip_funcs (v2) Add name that we can print out in kernel messages to aid in debugging. v2: drop DAL changes for upstream Signed-off-
drm/amd/amdgpu: Add name field to amd_ip_funcs (v2) Add name that we can print out in kernel messages to aid in debugging. v2: drop DAL changes for upstream Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
16a7989a |
| 28-Mar-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Drop print_status callbacks. First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the
drm/amd/amdgpu: Drop print_status callbacks. First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a3f1cf35 |
| 12-Apr-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: use max_dw in ring_init Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions.
drm/amdgpu: use max_dw in ring_init Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions. This fixes UVD with 8 concurrent submissions or more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c0365541 |
| 12-Apr-2016 |
Arindam Nath <arindam.nath@amd.com> |
drm/amdgpu: handle more than 10 UVD sessions (v2) Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all suppo
drm/amdgpu: handle more than 10 UVD sessions (v2) Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
be3ecca7 |
| 23-Mar-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6 This patch adds support for software clock gating to UVD 5 and UVD 6 blocks with a preliminary commented out hardware gatin
drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6 This patch adds support for software clock gating to UVD 5 and UVD 6 blocks with a preliminary commented out hardware gating routine. Currently hardware gating does not work so it's not activated. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3f99dd81 |
| 01-Apr-2016 |
Leo Liu <leo.liu@amd.com> |
drm/amdgpu: save and restore UVD context with suspend and resume and revert fix following it accordingly Revert "drm/amdgpu: stop trying to suspend UVD sessions v2" Revert "drm/
drm/amdgpu: save and restore UVD context with suspend and resume and revert fix following it accordingly Revert "drm/amdgpu: stop trying to suspend UVD sessions v2" Revert "drm/amdgpu: fix the UVD suspend sequence order" Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b61c0fc |
| 13-Mar-2016 |
Dave Airlie <airlied@redhat.com> |
Merge drm-fixes into drm-next. Nouveau wanted this to avoid some worse conflicts when I merge that.
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Revision tags: v4.4.5, v4.4.4, v4.4.3, openbmc-20160222-1, v4.4.2 |
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#
549300ce |
| 12-Feb-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/vi: move uvd tiling config setup into uvd code Split uvd and gfx programming. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <ale
drm/amdgpu/vi: move uvd tiling config setup into uvd code Split uvd and gfx programming. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: openbmc-20160212-1, openbmc-20160210-1 |
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#
d7af97db |
| 03-Feb-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: send UVD IB tests directly to the ring again We need the IB test for GPU resets as well and the scheduler should be stoped then. Signed-off-by: Christian König <chri
drm/amdgpu: send UVD IB tests directly to the ring again We need the IB test for GPU resets as well and the scheduler should be stoped then. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: openbmc-20160202-2, openbmc-20160202-1, v4.4.1 |
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#
9e5d5309 |
| 31-Jan-2016 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: make pad_ib a ring function v3 The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making
drm/amdgpu: make pad_ib a ring function v3 The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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