#
bdf84a80 |
| 14-Jan-2020 |
Joseph Greathouse <Joseph.Greathouse@amd.com> |
drm/amdgpu: Create generic DF struct in adev
The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF inf
drm/amdgpu: Create generic DF struct in adev
The only data fabric information the adev struct currently contains is a function pointer table. In the near future, we will be adding some cached DF information into adev. As such, this patch creates a new amdgpu_df struct for adev. Right now, it only containst the old function pointer table, but new stuff will be added soon.
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bdbe90f0 |
| 06-Jan-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/gmc: move invaliation bitmap setup to common code
So it can be shared with newer GMC versions.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christia
drm/amdgpu/gmc: move invaliation bitmap setup to common code
So it can be shared with newer GMC versions.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2ee9403e |
| 10-Dec-2019 |
Zhigang Luo <zhigang.luo@amd.com> |
drm/amd/amdgpu: L1 Policy(3/5) - removed ECC interrupt from VF
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.c
drm/amd/amdgpu: L1 Policy(3/5) - removed ECC interrupt from VF
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
08546895 |
| 02-Dec-2019 |
Zhigang Luo <zhigang.luo@amd.com> |
drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhub
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.D
drm/amd/amdgpu: L1 Policy(2/5) - removed GC GRBM violations from gfxhub
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
20bf2f6f |
| 14-Nov-2019 |
Zhigang Luo <zhigang.luo@amd.com> |
drm/amd/amdgpu: L1 Policy(1/5) - removed VM settings for mmhub and gfxhub from VF
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Den
drm/amd/amdgpu: L1 Policy(1/5) - removed VM settings for mmhub and gfxhub from VF
Signed-off-by: Zhigang Luo <zhigang.luo@amd.com> Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1e2c6d55 |
| 20-Dec-2019 |
John Clements <john.clements@amd.com> |
drm/amdgpu: Added ASIC specific check in gmc v9.0 ECC interrupt programming sequence
Devices newer then VEGA10/12 shall have these programming sequences performed by PSP BL
Reviewed-by: Hawking Zha
drm/amdgpu: Added ASIC specific check in gmc v9.0 ECC interrupt programming sequence
Devices newer then VEGA10/12 shall have these programming sequences performed by PSP BL
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
90f6452c |
| 10-Dec-2019 |
changzhu <Changfeng.Zhu@amd.com> |
drm/amdgpu: add invalidate semaphore limit for SRIOV and picasso in gmc9
It may fail to load guest driver in round 2 or cause Xstart problem when using invalidate semaphore for SRIOV or picasso. So
drm/amdgpu: add invalidate semaphore limit for SRIOV and picasso in gmc9
It may fail to load guest driver in round 2 or cause Xstart problem when using invalidate semaphore for SRIOV or picasso. So it needs avoid using invalidate semaphore for SRIOV and picasso.
Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
413fc385 |
| 09-Dec-2019 |
changzhu <Changfeng.Zhu@amd.com> |
drm/amdgpu: avoid using invalidate semaphore for picasso
It may cause timeout waiting for sem acquire in VM flush when using invalidate semaphore for picasso. So it needs to avoid using invalidate s
drm/amdgpu: avoid using invalidate semaphore for picasso
It may cause timeout waiting for sem acquire in VM flush when using invalidate semaphore for picasso. So it needs to avoid using invalidate semaphore for piasso.
Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4cf781c2 |
| 10-Dec-2019 |
John Clements <john.clements@amd.com> |
drm/amdgpu: Added RAS UMC error query support for Arcturus
Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: J
drm/amdgpu: Added RAS UMC error query support for Arcturus
Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
418899d6 |
| 09-Dec-2019 |
changzhu <Changfeng.Zhu@amd.com> |
drm/amdgpu: avoid using invalidate semaphore for picasso
It may cause timeout waiting for sem acquire in VM flush when using invalidate semaphore for picasso. So it needs to avoid using invalidate s
drm/amdgpu: avoid using invalidate semaphore for picasso
It may cause timeout waiting for sem acquire in VM flush when using invalidate semaphore for picasso. So it needs to avoid using invalidate semaphore for piasso.
Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f920d1bb |
| 18-Nov-2019 |
changzhu <Changfeng.Zhu@amd.com> |
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add sema
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation.
After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix.
Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
4ed8a037 |
| 18-Nov-2019 |
changzhu <Changfeng.Zhu@amd.com> |
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add sema
drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10
It may lose gpuvm invalidate acknowldege state across power-gating off cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire before invalidation and semaphore release after invalidation.
After adding semaphore acquire before invalidation, the semaphore register become read-only if another process try to acquire semaphore. Then it will not be able to release this semaphore. Then it may cause deadlock problem. If this deadlock problem happens, it needs a semaphore firmware fix.
Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f6c3623b |
| 19-Nov-2019 |
Dennis Li <Dennis.Li@amd.com> |
drm/amdgpu: implement querying ras error count for mmhub9.4
Get mmhub error counter by accessing EDC_CNT registers.
v2: Add mmhub_v9_4_ prefix for local static variable and function
Signed-off-by:
drm/amdgpu: implement querying ras error count for mmhub9.4
Get mmhub error counter by accessing EDC_CNT registers.
v2: Add mmhub_v9_4_ prefix for local static variable and function
Signed-off-by: Dennis Li <dennis.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9e612c11 |
| 13-Nov-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: init umc functions for arcturus umc ras
reuse vg20 umc functions for arcturus umc ras
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@a
drm/amdgpu: init umc functions for arcturus umc ras
reuse vg20 umc functions for arcturus umc ras
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6 |
|
#
f81b86a0 |
| 07-Oct-2019 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Enable gfx cache probing on HDP write for arcturus
This allows gfx cache to be probed and invalidated (for none-dirty cache lines) on a HDP write (from either another GPU or CPU). This s
drm/amdgpu: Enable gfx cache probing on HDP write for arcturus
This allows gfx cache to be probed and invalidated (for none-dirty cache lines) on a HDP write (from either another GPU or CPU). This should work only for the memory mapped as RW memory type newly added for arcturus, to achieve some cache coherence b/t multiple memory clients.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cb1545f7 |
| 07-Oct-2019 |
Oak Zeng <Oak.Zeng@amd.com> |
drm/amdgpu: Clean up gmc_v9_0_gart_enable
Many logic in this function are HDP set up, not gart set up. Moved those logic to gmc_v9_0_hw_init. No functional change.
Signed-off-by: Oak Zeng <Oak.Zeng
drm/amdgpu: Clean up gmc_v9_0_gart_enable
Many logic in this function are HDP set up, not gart set up. Moved those logic to gmc_v9_0_hw_init. No functional change.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Acked-by: Christian konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.5, v5.3.4, v5.3.3 |
|
#
ad02e08e |
| 02-Oct-2019 |
Ori Messinger <Ori.Messinger@amd.com> |
drm/amdgpu: Report vram vendor with sysfs (v3)
The vram vendor can be found as a separate sysfs file at: /sys/class/drm/card[X]/device/mem_info_vram_vendor The vram vendor is displayed as a string v
drm/amdgpu: Report vram vendor with sysfs (v3)
The vram vendor can be found as a separate sysfs file at: /sys/class/drm/card[X]/device/mem_info_vram_vendor The vram vendor is displayed as a string value.
v2: Use correct bit masking, and cache vram_vendor in gmc v3: Drop unused functions for vram width, type, and vendor
Signed-off-by: Ori Messinger <ori.messinger@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.2 |
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#
21889cec |
| 26-Sep-2019 |
Jack Zhang <Jack.Zhang1@amd.com> |
drm/amd/amdgpu/sriov ip block setting of Arcturus
Add ip block setting for Arcturus SRIOV
1.PSP need to be initialized before IH. 2.SMU doesn't need to be initialized at kmd driver. 3.Arcturus does
drm/amd/amdgpu/sriov ip block setting of Arcturus
Add ip block setting for Arcturus SRIOV
1.PSP need to be initialized before IH. 2.SMU doesn't need to be initialized at kmd driver. 3.Arcturus doesn't support DCE hardware,it needs to skip register access to DCE.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.1 |
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#
ba083492 |
| 18-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: implement common gmc_ras_late_init
common gmc_ecc_late_init can be shared among all generations of gmc
v2: rename gmc_ecc_late_init to gmc_ras_late_init
Signed-off-by: Tao Zhou <tao.zh
drm/amdgpu: implement common gmc_ras_late_init
common gmc_ecc_late_init can be shared among all generations of gmc
v2: rename gmc_ecc_late_init to gmc_ras_late_init
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3 |
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#
56c54b25 |
| 12-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: remove ih_info parameter of umc_ras_late_init
umc_ras_late_init can get the info by itself
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Sig
drm/amdgpu: remove ih_info parameter of umc_ras_late_init
umc_ras_late_init can get the info by itself
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2adf1344 |
| 12-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add common gmc_ras_fini function
gmc_ras_fini can be shared among all generations of gmc
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signe
drm/amdgpu: add common gmc_ras_fini function
gmc_ras_fini can be shared among all generations of gmc
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
65bc47a6 |
| 12-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: move mmhub_ras_if from gmc to mmhub block
mmhub_ras_if is relevant to mmhub
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Ale
drm/amdgpu: move mmhub_ras_if from gmc to mmhub block
mmhub_ras_if is relevant to mmhub
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d65bf1f8 |
| 12-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: replace mmhub_funcs with mmhub.funcs
remove mmhub_funcs in adev
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <a
drm/amdgpu: replace mmhub_funcs with mmhub.funcs
remove mmhub_funcs in adev
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
03740baa |
| 12-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: move umc_ras_if from gmc to umc block
umc_ras_if is relevant to umc
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deuche
drm/amdgpu: move umc_ras_if from gmc to umc block
umc_ras_if is relevant to umc
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
34cc4fd9 |
| 11-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: move umc ras irq functions to umc block
move umc ras irq functions from gmc v9 to generic umc block, these functions are relevant to umc and they can be shared among all generations of u
drm/amdgpu: move umc ras irq functions to umc block
move umc ras irq functions from gmc v9 to generic umc block, these functions are relevant to umc and they can be shared among all generations of umc
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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