#
667dfed9 |
| 27-Jul-2015 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
dmaengine: add a driver for Intel integrated DMA 64-bit
Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of LPSS devices such as HSUART or SPI. The iDMA IP is attached for
dmaengine: add a driver for Intel integrated DMA 64-bit
Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of LPSS devices such as HSUART or SPI. The iDMA IP is attached for private usage on each host controller independently.
While it has similarities with Synopsys DesignWare DMA, the following distinctions doesn't allow to use the existing driver: - 64-bit mode with corresponding changes in Hardware Linked List data structure - many slight differences in the channel registers
Moreover this driver is based on the DMA virtual channels framework that helps to make the driver cleaner and easy to understand.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Revision tags: v4.2-rc1, v4.1, v4.1-rc8, v4.1-rc7, v4.1-rc6, v4.1-rc5, v4.1-rc4, v4.1-rc3 |
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#
e3fa9841 |
| 05-May-2015 |
Jun Nie <jun.nie@linaro.org> |
dmaengine: zxdma: Support ZTE ZX296702 dma
Add ZTE ZX296702 dma controller support. Only device tree probe is support currently.
Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Maxime Ripa
dmaengine: zxdma: Support ZTE ZX296702 dma
Add ZTE ZX296702 dma controller support. Only device tree probe is support currently.
Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
a57e16cf |
| 25-May-2015 |
Robert Jarzmik <robert.jarzmik@free.fr> |
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching)
dmaengine: pxa: add pxa dmaengine driver
This is a new driver for pxa SoCs, which is also compatible with the former mmp_pdma.
The rationale behind a new driver (as opposed to incremental patching) was :
- the new driver relies on virt-dma, which obsoletes all the internal structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the functions
- mmp_pdma allocates dma coherent descriptors containing not only hardware descriptors but linked list information The new driver only puts the dma hardware descriptors (ie. 4 u32) into the dma pool allocated memory. This changes completely the way descriptors are handled
- the architecture behind the interrupt/tasklet management was rewritten to be more conforming to virt-dma
- the buffers alignment is handled differently The former driver assumed that the DMA channel stopped between each descriptor. The new one chains descriptors to let the channel running. This is a necessary guarantee for real-time high bandwidth usecases such as video capture on "old" architectures such as pxa.
- hot chaining / cold chaining / no chaining Whenever possible, submitting a descriptor "hot chains" it to a running channel. There is still no guarantee that the descriptor will be issued, as the channel might be stopped just before the descriptor is submitted. Yet this allows to submit several video buffers, and resubmit a buffer while another is under handling. As before, dma_async_issue_pending() is the only guarantee to have all the buffers issued. When an alignment issue is detected (ie. one address in a descriptor is not a multiple of 8), if the already running channel is in "aligned mode", the channel will stop, and restarted in "misaligned mode" to finished the issued list.
- descriptors reusing A submitted, issued and completed descriptor can be reused, ie resubmitted if it was prepared with the proper flag (DMA_PREP_ACK). Only a channel resources release will in this case release that buffer. This allows a rolling ring of buffers to be reused, where there are several thousands of hardware descriptors used (video buffer for example).
Additionally, a set of more casual features is introduced : - debugging traces - lockless way to know if a descriptor is terminated or not
The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x), with dmatest, pxa_camera and pxamci.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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Revision tags: v4.1-rc2, v4.1-rc1, v4.0 |
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#
a074ae38 |
| 09-Apr-2015 |
Peter Ujfalusi <peter.ujfalusi@ti.com> |
dmaengine: Add driver for TI DMA crossbar on DRA7x
The DRA7x has more peripherals with DMA requests than the sDMA can handle: 205 vs 127. All DMA requests are routed through the DMA crossbar, which
dmaengine: Add driver for TI DMA crossbar on DRA7x
The DRA7x has more peripherals with DMA requests than the sDMA can handle: 205 vs 127. All DMA requests are routed through the DMA crossbar, which can be configured to route selected incoming DMA requests to specific sDMA request.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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Revision tags: v4.0-rc7, v4.0-rc6, v4.0-rc5, v4.0-rc4, v4.0-rc3, v4.0-rc2 |
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#
ad80da65 |
| 03-Mar-2015 |
Xuelin Shi <xuelin.shi@freescale.com> |
dmaengine: Driver support for FSL RaidEngine device.
The RaidEngine is a new FSL hardware used for Raid5/6 acceration. This patch enables the RaidEngine functionality and provides hardware offloadin
dmaengine: Driver support for FSL RaidEngine device.
The RaidEngine is a new FSL hardware used for Raid5/6 acceration. This patch enables the RaidEngine functionality and provides hardware offloading capability for memcpy, xor and pq computation. It works with async_tx.
Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
9f2fd0df |
| 18-Mar-2015 |
Rameshwar Prasad Sahu <rsahu@apm.com> |
dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA op
dmaengine: Add support for APM X-Gene SoC DMA engine driver
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene SoC DMA engine consists of 4 DMA channels for performing DMA operations. These DMA operations include memory copy, scatter-gather memory copy, raid5 xor, and raid6 p+q offloading.
Signed-off-by: Rameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
d894fc60 |
| 18-Mar-2015 |
Alex Smith <alex.smith@imgtec.com> |
dmaengine: jz4780: add driver for the Ingenic JZ4780 DMA controller
This patch adds a driver for the DMA controller found in the Ingenic JZ4780.
It currently does not implement any support for the
dmaengine: jz4780: add driver for the Ingenic JZ4780 DMA controller
This patch adds a driver for the DMA controller found in the Ingenic JZ4780.
It currently does not implement any support for the programmable firmware feature of the controller - this is not necessary for most uses. It also does not take priority into account when allocating channels, it just allocates the first available channel. This can be implemented later.
Signed-off-by: Alex Smith <alex.smith@imgtec.com> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> [Updated for dmaengine api changes, Add residue support, couple of minor fixes] Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
36111da7 |
| 09-Mar-2015 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
dmaengine: intel-mid-dma: remove the driver
Since the last and the only user of this driver is converted to use dw_dmac we can remove driver from the tree.
Moreover, besides the driver is unmaintai
dmaengine: intel-mid-dma: remove the driver
Since the last and the only user of this driver is converted to use dw_dmac we can remove driver from the tree.
Moreover, besides the driver is unmaintained a long time, it serves for the DesignWare DMA IP, for which we have already driver in the tree.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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#
2b49e0c5 |
| 23-Feb-2015 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
dmaengine: append hsu DMA driver
The HSU DMA is developed to support High Speed UART controllers found in particular on Intel MID platforms such as Intel Medfield.
The existing implementation is ti
dmaengine: append hsu DMA driver
The HSU DMA is developed to support High Speed UART controllers found in particular on Intel MID platforms such as Intel Medfield.
The existing implementation is tighten to the drivers/tty/serial/mfd.c driver and has a lot of disadvantages. Besides that we would like to get rid of the old HS UART driver in regarding to extending the 8250 which supports generic DMAEngine API. That's why the current driver has been developed.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v4.0-rc1, v3.19, v3.19-rc7, v3.19-rc6, v3.19-rc5, v3.19-rc4, v3.19-rc3, v3.19-rc2, v3.19-rc1 |
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#
5689ba7f |
| 11-Dec-2014 |
Andrew Bresticker <abrestic@chromium.org> |
dmaengine: Add driver for IMG MDC
Add support for the IMG Multi-threaded DMA Controller (MDC) found on certain IMG SoCs. Currently this driver supports the variant present on the MIPS-based Pistach
dmaengine: Add driver for IMG MDC
Add support for the IMG Multi-threaded DMA Controller (MDC) found on certain IMG SoCs. Currently this driver supports the variant present on the MIPS-based Pistachio SoC.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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Revision tags: v3.18, v3.18-rc7, v3.18-rc6, v3.18-rc5, v3.18-rc4, v3.18-rc3, v3.18-rc2, v3.18-rc1, v3.17, v3.17-rc7, v3.17-rc6, v3.17-rc5, v3.17-rc4, v3.17-rc3, v3.17-rc2, v3.17-rc1, v3.16, v3.16-rc7, v3.16-rc6, v3.16-rc5 |
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#
87244fe5 |
| 08-Jul-2014 |
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
dmaengine: rcar-dmac: Add Renesas R-Car Gen2 DMA Controller (DMAC) driver
The DMAC is a general purpose multi-channel DMA controller that supports both slave and memcpy transfers.
The driver curren
dmaengine: rcar-dmac: Add Renesas R-Car Gen2 DMA Controller (DMAC) driver
The DMAC is a general purpose multi-channel DMA controller that supports both slave and memcpy transfers.
The driver currently supports the DMAC found in the r8a7790 and r8a7791 SoCs. Support for compatible DMA controllers (such as the audio DMAC) will be added later.
Feature-wise, automatic hardware handling of descriptors chains isn't supported yet. LPAE support is implemented.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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#
e1f7c9ee |
| 22-Oct-2014 |
Ludovic Desroches <ludovic.desroches@atmel.com> |
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver
New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices.
Signed-off-by: Ludovic Desroches <ludovic.desroch
dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver
New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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Revision tags: v3.16-rc4, v3.16-rc3, v3.16-rc2, v3.16-rc1, v3.15, v3.15-rc8, v3.15-rc7, v3.15-rc6, v3.15-rc5, v3.15-rc4, v3.15-rc3, v3.15-rc2, v3.15-rc1, v3.14, v3.14-rc8, v3.14-rc7, v3.14-rc6, v3.14-rc5, v3.14-rc4, v3.14-rc3, v3.14-rc2, v3.14-rc1, v3.13, v3.13-rc8, v3.13-rc7 |
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#
7bced397 |
| 30-Dec-2013 |
Dan Williams <dan.j.williams@intel.com> |
net_dma: simple removal
Per commit "77873803363c net_dma: mark broken" net_dma is no longer used and there is no plan to fix it.
This is the mechanical removal of bits in CONFIG_NET_DMA ifdef guard
net_dma: simple removal
Per commit "77873803363c net_dma: mark broken" net_dma is no longer used and there is no plan to fix it.
This is the mechanical removal of bits in CONFIG_NET_DMA ifdef guards. Reverting the remainder of the net_dma induced changes is deferred to subsequent patches.
Marked for stable due to Roman's report of a memory leak in dma_pin_iovec_pages():
https://lkml.org/lkml/2014/9/3/177
Cc: Dave Jiang <dave.jiang@intel.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: David Whipple <whipple@securedatainnovations.ch> Cc: Alexander Duyck <alexander.h.duyck@intel.com> Cc: <stable@vger.kernel.org> Reported-by: Roman Gushchin <klamm@yandex-team.ru> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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#
b45b262c |
| 19-Jul-2014 |
Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
dmaengine: add a driver for AMBA AXI NBPF DMAC IP cores
This patch adds a driver for NBPF DMAC IP cores from Renesas, designed for the AMBA AXI bus.
Signed-off-by: Guennadi Liakhovetski <g.liakhove
dmaengine: add a driver for AMBA AXI NBPF DMAC IP cores
This patch adds a driver for NBPF DMAC IP cores from Renesas, designed for the AMBA AXI bus.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
55585930 |
| 17-Jul-2014 |
Maxime Ripard <maxime.ripard@free-electrons.com> |
dmaengine: sun6i: Add driver for the Allwinner A31 DMA controller
The Allwinner A31 has a 16 channels DMA controller that it shares with the newer A23. Although sharing some similarities with the DM
dmaengine: sun6i: Add driver for the Allwinner A31 DMA controller
The Allwinner A31 has a 16 channels DMA controller that it shares with the newer A23. Although sharing some similarities with the DMA controller of the older Allwinner SoCs, it's significantly different, I don't expect it to be possible to share the driver for these two.
The A31 Controller is able to memory-to-memory or memory-to-device transfers on the 16 channels in parallel.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
653e67f7 |
| 14-Jul-2014 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
dmaengine: inherit debug settings from the subsystem for subdirectories
To be able to see debug messages during boot, enable the debug settings from Kconfig also for drivers in subdirectories.
Sign
dmaengine: inherit debug settings from the subsystem for subdirectories
To be able to see debug messages during boot, enable the debug settings from Kconfig also for drivers in subdirectories.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
95b4ecbf |
| 11-Jul-2014 |
Siva Yerramreddy <yshivakrishna@gmail.com> |
dma: MIC X100 DMA Driver
This patch implements DMA Engine API for DMA controller on MIC X100 Coprocessors. DMA h/w is shared between host and card s/w. Channels 0 to 3 are used by host and 4 to 7 ar
dma: MIC X100 DMA Driver
This patch implements DMA Engine API for DMA controller on MIC X100 Coprocessors. DMA h/w is shared between host and card s/w. Channels 0 to 3 are used by host and 4 to 7 are used by card. Since the DMA device doesn't show up as PCIe device, a virtual bus called mic bus is created and virtual devices are added on that bus to follow device model. Allowed dma transfer directions are host to card, card to host and card to card.
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Nikhil Rao <nikhil.rao@intel.com> Reviewed-by: Sudeep Dutt <sudeep.dutt@intel.com> Signed-off-by: Siva Yerramreddy <yshivakrishna@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
9cd4360d |
| 23-Apr-2014 |
Srikanth Thokala <sthokal@xilinx.com> |
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- ban
dma: Add Xilinx AXI Video Direct Memory Access Engine driver support
This is the driver for the AXI Video Direct Memory Access (AXI VDMA) core, which is a soft Xilinx IP core that provides high- bandwidth direct memory access between memory and AXI4-Stream type video target peripherals. The core provides efficient two dimensional DMA operations with independent asynchronous read and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Levente Kurusa <levex@linux.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
e7c0fe2a |
| 29-Mar-2014 |
Andy Gross <agross@codeaurora.org> |
dmaengine: add Qualcomm BAM dma driver
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a speci
dmaengine: add Qualcomm BAM dma driver
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each channel provides a uni-directional data transfer engine that is capable of transferring data between the peripheral and system memory (System mode), or between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between peripherals and system memory.
Signed-off-by: Andy Gross <agross@codeaurora.org> Tested-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
d6be34fb |
| 17-Feb-2014 |
Jingchang Lu <b35083@freescale.com> |
dma: Add Freescale eDMA engine driver support
Add Freescale enhanced direct memory(eDMA) controller support. This module can be found on Vybrid and LS-1 SoCs.
Signed-off-by: Alison Wang <b18965@fre
dma: Add Freescale eDMA engine driver support
Add Freescale enhanced direct memory(eDMA) controller support. This module can be found on Vybrid and LS-1 SoCs.
Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Jingchang Lu <b35083@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
5f9e685a |
| 17-Jan-2014 |
Jonas Jensen <jonas.jensen@gmail.com> |
dmaengine: Add MOXA ART DMA engine driver
The MOXA ART SoC has a DMA controller capable of offloading expensive memory operations, such as large copies. This patch adds support for the controller in
dmaengine: Add MOXA ART DMA engine driver
The MOXA ART SoC has a DMA controller capable of offloading expensive memory operations, such as large copies. This patch adds support for the controller including four channels. Two of these are used to handle MMC copy on the UC-7112-LX hardware. The remaining two can be used in a future audio driver or client application.
Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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#
96286b57 |
| 06-Jan-2014 |
Florian Meier <florian.meier@koalo.de> |
dmaengine: Add support for BCM2835
Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA.
Signed-off-by: Florian Meier <florian.meier@koalo.de
dmaengine: Add support for BCM2835
Add support for DMA controller of BCM2835 as used in the Raspberry Pi. Currently it only supports cyclic DMA.
Signed-off-by: Florian Meier <florian.meier@koalo.de> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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Revision tags: v3.13-rc6, v3.13-rc5, v3.13-rc4, v3.13-rc3, v3.13-rc2, v3.13-rc1, v3.12, v3.12-rc7, v3.12-rc6, v3.12-rc5 |
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#
ddeccb8d |
| 07-Oct-2013 |
Heiko Stuebner <heiko@sntech.de> |
dmaengine: add driver for Samsung s3c24xx SoCs
This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run.
Conceptually the
dmaengine: add driver for Samsung s3c24xx SoCs
This adds a new driver to support the s3c24xx dma using the dmaengine and makes the old one in mach-s3c24xx obsolete in the long run.
Conceptually the s3c24xx-dma feels like a distant relative of the pl08x with numerous virtual channels being mapped to a lot less physical ones. The driver therefore borrows a lot from the amba-pl08x driver in this regard. Functionality-wise the driver gains a memcpy ability in addition to the slave_sg one.
The driver supports both the method for requesting the peripheral used by SoCs before the S3C2443 and the different method for S3C2443 and later.
On earlier SoCs the hardware channels usable for specific peripherals is constrainted while on later SoCs all channels can be used for any peripheral.
Tested on a s3c2416-based board, memcpy using the dmatest module and slave_sg partially using the spi-s3c64xx driver.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Revision tags: v3.12-rc4, v3.12-rc3, v3.12-rc2, v3.12-rc1, v3.11 |
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#
8e6152bc |
| 26-Aug-2013 |
Zhangfei Gao <zhangfei.gao@linaro.org> |
dmaengine: Add hisilicon k3 DMA engine driver
Add dmaengine driver for hisilicon k3 platform based on virt_dma
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Kai Yang <jean.yangka
dmaengine: Add hisilicon k3 DMA engine driver
Add dmaengine driver for hisilicon k3 platform based on virt_dma
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Kai Yang <jean.yangkai@huawei.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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Revision tags: v3.11-rc7, v3.11-rc6, v3.11-rc5, v3.11-rc4, v3.11-rc3, v3.11-rc2, v3.11-rc1, v3.10, v3.10-rc7 |
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#
9b3452d1 |
| 20-Jun-2013 |
Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
usb: musb dma: add cppi41 dma driver
This driver is currently used by musb' cppi41 couter part. I may merge both dma engine user of musb at some point but not just yet.
The driver seems to work in
usb: musb dma: add cppi41 dma driver
This driver is currently used by musb' cppi41 couter part. I may merge both dma engine user of musb at some point but not just yet.
The driver seems to work in RX/TX mode in host mode, tested on mass storage. I increaed the size of the TX / RX transfers and waited for the core code to cancel a transfers and it seems to recover.
v2..3: - use mall transfers on RX side and check data toggle. - use rndis mode on tx side so we haveon interrupt for 4096 transfers. - remove custom "transferred" hack and use dmaengine_tx_status() to compute the total amount of data that has been transferred. - cancel transfers and reclaim descriptors
v1..v2: - RX path added - dma mode 0 & 1 is working - device tree nodes re-created.
Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <djbw@fb.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
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