#
a9c9147e |
| 26-Nov-2009 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: dma-mapping: provide per-cpu type map/unmap functions Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Tested-By: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
#
548c6af4 |
| 30-Dec-2009 |
Haojian Zhuang <haojian.zhuang@marvell.com> |
[ARM] pxa: enable L2 if present in XSC3 Check whether L2 is present or not in XSC3. If it's present, enable L2 immediately. Disabling L2 after L2 is enabled that would result in
[ARM] pxa: enable L2 if present in XSC3 Check whether L2 is present or not in XSC3. If it's present, enable L2 immediately. Disabling L2 after L2 is enabled that would result in unpredicatable behavior of XSC3 processor. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
show more ...
|
#
2c9b9c84 |
| 26-Nov-2009 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: add size argument to __cpuc_flush_dcache_page ... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.u
ARM: add size argument to __cpuc_flush_dcache_page ... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.32-rc8, v2.6.32-rc7, v2.6.32-rc6 |
|
#
345a3229 |
| 29-Oct-2009 |
Mikael Pettersson <mikpe@it.uu.se> |
iop: implement sched_clock() This adds a better sched_clock() to the IOP platform, implemented using its new clocksource support. Tested on n2100, compile-tested for all plat-io
iop: implement sched_clock() This adds a better sched_clock() to the IOP platform, implemented using its new clocksource support. Tested on n2100, compile-tested for all plat-iop machines. [dan.j.williams@intel.com: allow early cp6 access] Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
show more ...
|
Revision tags: v2.6.32-rc5, v2.6.32-rc4, v2.6.32-rc3, v2.6.32-rc1, v2.6.32-rc2 |
|
#
4fb28474 |
| 25-Sep-2009 |
Kirill A. Shutemov <kirill@shutemov.name> |
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It
ARM: 5727/1: Pass IFSR register to do_PrefetchAbort() Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.31, v2.6.31-rc9, v2.6.31-rc8, v2.6.31-rc7, v2.6.31-rc6, v2.6.31-rc5, v2.6.31-rc4, v2.6.31-rc3, v2.6.31-rc2, v2.6.31-rc1, v2.6.30, v2.6.30-rc8, v2.6.30-rc7, v2.6.30-rc6, v2.6.30-rc5, v2.6.30-rc4, v2.6.30-rc3, v2.6.30-rc2, v2.6.30-rc1, v2.6.29, v2.6.29-rc8, v2.6.29-rc7, v2.6.29-rc6, v2.6.29-rc5, v2.6.29-rc4, v2.6.29-rc3, v2.6.29-rc2, v2.6.29-rc1, v2.6.28, v2.6.28-rc9, v2.6.28-rc8, v2.6.28-rc7 |
|
#
59c7bcd4 |
| 29-Nov-2008 |
Eric Miao <eric.miao@marvell.com> |
[ARM] pxa: add base PXA935 support due to CPUID change PXA935 has changed its implementor ID from Intel to Marvell, this patch modifies arch/arm/boot/compressed/head.S and proc-xsc3.S to
[ARM] pxa: add base PXA935 support due to CPUID change PXA935 has changed its implementor ID from Intel to Marvell, this patch modifies arch/arm/boot/compressed/head.S and proc-xsc3.S to support a smooth bootup. Signed-off-by: Eric Miao <eric.miao@marvell.com>
show more ...
|
Revision tags: v2.6.28-rc6, v2.6.28-rc5, v2.6.28-rc4, v2.6.28-rc3, v2.6.28-rc2 |
|
#
6bee00db |
| 24-Oct-2008 |
Dan Williams <dan.j.williams@intel.com> |
[ARM] xsc3: revert writethrough memory-type encoding change Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was fingered by git-bisect for a boot failure on iop13xx. The
[ARM] xsc3: revert writethrough memory-type encoding change Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was fingered by git-bisect for a boot failure on iop13xx. The change made L_PTE_MT_WRITETHROUGH mappings L2-uncacheable. Russell points out that this mapping is used for the vector page. Given the regression, and the fact this page is used often, restore the old behaviour. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
show more ...
|
Revision tags: v2.6.28-rc1, v2.6.27, v2.6.27-rc9, v2.6.27-rc8, v2.6.27-rc7, v2.6.27-rc6 |
|
#
5ec9407d |
| 07-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Don't include asm/elf.h in asm code asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
db5b7169 |
| 07-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Remove MT_DEVICE_IXP2000 and associated definitions As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert
[ARM] Remove MT_DEVICE_IXP2000 and associated definitions As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
#
40df2d1d |
| 07-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Update Xscale and Xscale3 PTE mappings Use 'shared device' mappings for devices, and use the standard bit combinations for Xscale3. Signed-off-by: Russell King <rmk+kernel
[ARM] Update Xscale and Xscale3 PTE mappings Use 'shared device' mappings for devices, and use the standard bit combinations for Xscale3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
#
639b0ae7 |
| 06-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Convert ARMv6 and ARMv7 to use new memory types Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
9e8b5199 |
| 06-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Convert Xscale and Xscale3 to use new memory types Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
da091653 |
| 06-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Convert set_pte_ext implementions to macros There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S fi
[ARM] Convert set_pte_ext implementions to macros There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.27-rc5, v2.6.27-rc4, v2.6.27-rc3, v2.6.27-rc2 |
|
#
a09e64fb |
| 05-Aug-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
#
be509729 |
| 04-Aug-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Remove asm/hardware.h, use asm/arch/hardware.h instead Remove includes of asm/hardware.h in addition to asm/arch/hardware.h. Then, since asm/hardware.h only exists to include asm/a
[ARM] Remove asm/hardware.h, use asm/arch/hardware.h instead Remove includes of asm/hardware.h in addition to asm/arch/hardware.h. Then, since asm/hardware.h only exists to include asm/arch/hardware.h, update everything to directly include asm/arch/hardware.h and remove asm/hardware.h. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.27-rc1, v2.6.26, v2.6.26-rc9, v2.6.26-rc8, v2.6.26-rc7, v2.6.26-rc6 |
|
#
905a09d5 |
| 06-Jun-2008 |
Eric Miao <eric.miao@marvell.com> |
[ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2) (20072fd0c93349e19527dd2fa9588b4335960e62 lost most of its changes somehow, came from a mbox archive applied with git-am.
[ARM] pxa: add support for L2 outer cache on XScale3 (attempt 2) (20072fd0c93349e19527dd2fa9588b4335960e62 lost most of its changes somehow, came from a mbox archive applied with git-am. No idea what happened. This puts back the missing bits. --rmk) The initial patch from Lothar, and Lennert make it into a cleaner one, modified and tested on PXA320 by Eric Miao. This patch moves the L2 cache operations out of proc-xsc3.S into dedicated outer cache support code. CACHE_XSC3L2 can be deselected so no L2 cache specific code will be linked in, and that L2 enable bit will not be set, this applies to the following cases: a. _only_ PXA300/PXA310 support included and no L2 cache wanted b. PXA320 support included, but want L2 be disabled So the enabling of L2 depends on two things: - CACHE_XSC3L2 is selected - and L2 cache is present Where the latter is only a safeguard (previous testing shows it works OK even when this bit is turned on). IXP series of processors with XScale3 cannot disable L2 cache for the moment since they depend on the L2 cache for its coherent memory, so IXP may always select CACHE_XSC3L2. Other L2 relevant bits are always turned on (i.e. the original code enclosed by #if L2_CACHE_ENABLED .. #endif), as they showed no side effects. Specifically, these bits are: - OC bits in TTBASE register (table walk outer cache attributes) - LLR Outer Cache Attributes (OC) in Auxiliary Control Register Signed-off-by: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.26-rc5, v2.6.26-rc4, v2.6.26-rc3, v2.6.26-rc2, v2.6.26-rc1 |
|
#
4a1fd556 |
| 21-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in th
[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.25, v2.6.25-rc9, v2.6.25-rc8, v2.6.25-rc7, v2.6.25-rc6, v2.6.25-rc5, v2.6.25-rc4, v2.6.25-rc3, v2.6.25-rc2, v2.6.25-rc1, v2.6.24, v2.6.24-rc8, v2.6.24-rc7, v2.6.24-rc6, v2.6.24-rc5, v2.6.24-rc4, v2.6.24-rc3, v2.6.24-rc2, v2.6.24-rc1, v2.6.23, v2.6.23-rc9, v2.6.23-rc8, v2.6.23-rc7, v2.6.23-rc6, v2.6.23-rc5, v2.6.23-rc4, v2.6.23-rc3, v2.6.23-rc2, v2.6.23-rc1, v2.6.22, v2.6.22-rc7, v2.6.22-rc6, v2.6.22-rc5, v2.6.22-rc4, v2.6.22-rc3, v2.6.22-rc2, v2.6.22-rc1, v2.6.21, v2.6.21-rc7, v2.6.21-rc6, v2.6.21-rc5, v2.6.21-rc4, v2.6.21-rc3, v2.6.21-rc2, v2.6.21-rc1 |
|
#
850b4293 |
| 04-Feb-2007 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 4123/1: xsc3: general cleanup This patch cleans up proc-xsc3: - Correct a number of typos. - Fix up indentation in a number of places. - Change references to the various ca
[ARM] 4123/1: xsc3: general cleanup This patch cleans up proc-xsc3: - Correct a number of typos. - Fix up indentation in a number of places. - Change references to the various caches to be more clear about whether we're talking about the L1 D, the L1 I or the unified L2 cache. - Rename "drain write buffer" to "data write barrier", the official name used in the Manzano manual. - Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based processor". Also, since a previously merged patch implements proper support for using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer need to enable access to CP0 on boot. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.20, v2.6.20-rc7, v2.6.20-rc6, v2.6.20-rc5, v2.6.20-rc4, v2.6.20-rc3, v2.6.20-rc2 |
|
#
57fee39f |
| 19-Dec-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 4061/1: xsc3: change of maintainer Deepak Saxena has agreed to hand xsc3 maintainership over to me. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by
[ARM] 4061/1: xsc3: change of maintainer Deepak Saxena has agreed to hand xsc3 maintainership over to me. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.20-rc1 |
|
#
ad1ae2fe |
| 13-Dec-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Unuse another Linux PTE bit L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ex
[ARM] Unuse another Linux PTE bit L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
#
f5236225 |
| 01-Dec-2006 |
Dan Williams <dan.j.williams@intel.com> |
[ARM] 3967/1: xsc3: make branch predication configurable on xsc3 Remove BTB_ENABLE from proc-xsc3.S On some early revisions of xsc3 enabling the branch target buffer can cause c
[ARM] 3967/1: xsc3: make branch predication configurable on xsc3 Remove BTB_ENABLE from proc-xsc3.S On some early revisions of xsc3 enabling the branch target buffer can cause crashes, see erratum #42. Cc: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
#
0e5fdca7 |
| 01-Dec-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3971/1: xsc3: get rid of L_PTE_COHERENT Merge L_PTE_COHERENT with L_PTE_SHARED and free up a L_PTE_* bit. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-
[ARM] 3971/1: xsc3: get rid of L_PTE_COHERENT Merge L_PTE_COHERENT with L_PTE_SHARED and free up a L_PTE_* bit. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
Revision tags: v2.6.19, v2.6.19-rc6 |
|
#
ee90dabc |
| 09-Nov-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Include asm/elf.h instead of asm/procinfo.h These files want to provide/access ELF hwcap information, so should be including asm/elf.h rather than asm/procinfo.h Signed-of
[ARM] Include asm/elf.h instead of asm/procinfo.h These files want to provide/access ELF hwcap information, so should be including asm/elf.h rather than asm/procinfo.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|
#
3f8efdbe |
| 01-Jul-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
Merge nommu branch
|
Revision tags: v2.6.19-rc5, v2.6.19-rc4, v2.6.19-rc3, v2.6.19-rc2, v2.6.19-rc1, v2.6.18, v2.6.18-rc7, v2.6.18-rc6, v2.6.18-rc5, v2.6.18-rc4, v2.6.18-rc3, v2.6.18-rc2, v2.6.18-rc1 |
|
#
8799ee9f |
| 29-Jun-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Set bit 4 on section mappings correctly depending on CPU On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to b
[ARM] Set bit 4 on section mappings correctly depending on CPU On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
show more ...
|