[ARM] Feroceon: speed up flushing of the entire cache

Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as

[ARM] Feroceon: speed up flushing of the entire cache

Flushing the L1 D cache with a test/clean/invalidate loop is very
easy in software, but it is not the quickest way of doing it, as
there is a lot of overhead involved in re-scanning the cache from
the beginning every time we hit a dirty line.

This patch makes proc-feroceon.S use "clean+invalidate by set/way"
loops according to possible cache configuration of Feroceon CPUs
(either direct-mapped or 4-way set associative).

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

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[ARM] Feroceon: annotate 88fr531-vd CPU entries

Annotate the entries for the 88fr531-vd CPU core in
arch/arm/boot/compressed/head.S and arch/arm/mm/proc-feroceon.S
with the full name

[ARM] Feroceon: annotate 88fr531-vd CPU entries

Annotate the entries for the 88fr531-vd CPU core in
arch/arm/boot/compressed/head.S and arch/arm/mm/proc-feroceon.S
with the full name of the core.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <linux@arm.linux.org.uk>

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[ARM] Orion: fix various whitespace and coding style issues

More cosmetic cleanup:
- Replace 8-space indents by proper tab indents.
- In structure initialisers, use a trailing comma

[ARM] Orion: fix various whitespace and coding style issues

More cosmetic cleanup:
- Replace 8-space indents by proper tab indents.
- In structure initialisers, use a trailing comma for every member.
- Collapse "},\n{" in structure initialiers to "}, {".

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <linux@arm.linux.org.uk>

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[ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()

This patch implements a set of Feroceon-specific
{copy,clear}_user_page() routines that perform more optima

[ARM] Feroceon: Feroceon-specific WA-cache compatible {copy,clear}_user_page()

This patch implements a set of Feroceon-specific
{copy,clear}_user_page() routines that perform more optimally than
the generic implementations. This also deals with write-allocate
caches (Feroceon can run L1 D in WA mode) which otherwise prevents
Linux from booting.

[nico: optimized the code even further]

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
Tested-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

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[ARM] Feroceon: fix function alignment in proc-feroceon.S

One overzealous .align 10 fixed, and a few .align5 added.

Signed-off-by: Nicolas Pitre <nico@marvell.com>

[ARM] feroceon: remove CONFIG_CPU_CACHE_ROUND_ROBIN check

Since the Feroceon cache replacement policy is always pseudorandom
(and the relevant control register bit is ignored), remove th

[ARM] feroceon: remove CONFIG_CPU_CACHE_ROUND_ROBIN check

Since the Feroceon cache replacement policy is always pseudorandom
(and the relevant control register bit is ignored), remove the
CONFIG_CPU_CACHE_ROUND_ROBIN check from proc-feroceon.S.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

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[ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check

Since the Feroceon doesn't have a global WT override bit like
ARM926 does, remove all code relating to this mode of operation

[ARM] feroceon: remove CONFIG_CPU_DCACHE_WRITETHROUGH check

Since the Feroceon doesn't have a global WT override bit like
ARM926 does, remove all code relating to this mode of operation
from proc-feroceon.S.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

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[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f

The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in th

[ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84f

The proc-*.S files have the _prefetch_abort pointer placed at the end
of the processor structure but the cpu-multi32.h defines it in the
second position. The patch also fixes the support for XSC3 and the
MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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Add a prefetch abort handler

This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with

Add a prefetch abort handler

This patch adds a prefetch abort handler similar to the data abort one
and renames the latter for consistency. Initial implementation by Paul
Brook with some renaming by Catalin Marinas.

Signed-off-by: Paul Brook <paul@codesourcery.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

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[ARM] Feroceon: support old cores with ARM926 ID

This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and old

[ARM] Feroceon: support old cores with ARM926 ID

This enables the usage of some old Feroceon cores
for which the CPU ID is equal to the ARM926 ID.
Relevant for Feroceon-1850 and old Feroceon-2850.

Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>

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[ARM] Marvell Feroceon CPU core support

The Feroceon is a family of independent ARMv5TE compliant CPU core
implementations, supporting a variable depth pipeline and out-of-order
exec

[ARM] Marvell Feroceon CPU core support

The Feroceon is a family of independent ARMv5TE compliant CPU core
implementations, supporting a variable depth pipeline and out-of-order
execution. The Feroceon is configurable with VFP support, and the
later models in the series are superscalar with up to two instructions
per clock cycle.

This patch adds the initial low-level cache/TLB handling for this core.

Signed-off-by: Assaf Hoffman <hoffman@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>

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