ARM: 8296/1: cache-l2x0: clean up aurora cache handling

The aurora cache controller is the only remaining user of a couple
of functions in this file and are completely unused when that is
disabled,

ARM: 8296/1: cache-l2x0: clean up aurora cache handling

The aurora cache controller is the only remaining user of a couple
of functions in this file and are completely unused when that is
disabled, leading to build warnings:

arch/arm/mm/cache-l2x0.c:167:13: warning: 'l2x0_cache_sync' defined but not used [-Wunused-function]
arch/arm/mm/cache-l2x0.c:184:13: warning: 'l2x0_flush_all' defined but not used [-Wunused-function]
arch/arm/mm/cache-l2x0.c:194:13: warning: 'l2x0_disable' defined but not used [-Wunused-function]

With the knowledge that the code is now aurora-specific, we can
simplify it noticeably:

- The pl310 errata workarounds are not needed on aurora and can be removed
- As confirmed by Thomas Petazzoni from the data sheet, the cache_wait()
macro is never needed.
- No need to hold the lock across atomic cache sync
- We can load the l2x0_base into a local variable across operations

There should be no functional change in this patch, but readability
and the generated object code improves, along with avoiding the
warnings.

(on Armada 370 RD and Armada XP GP, boot tested, plus a little bit of
DMA traffic by reading data from a SD card)

Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: cache-l2x0.c: Make it clear that cache-l2x0 handles L310 cache controller

It is not clear from the filename, and comment at the begining adds to the
confusion by not listing L310. Fix it.

Sign

ARM: cache-l2x0.c: Make it clear that cache-l2x0 handles L310 cache controller

It is not clear from the filename, and comment at the begining adds to the
confusion by not listing L310. Fix it.

Signed-off-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>

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ARM: l2c: fix comment

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Jiri Kosina <jkosi

ARM: l2c: fix comment

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Jiri Kosina <jkosina@suse.cz>

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ARM: 8262/1: l2c: Add support for overriding prefetch settings

Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C

ARM: 8262/1: l2c: Add support for overriding prefetch settings

Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and necessary support in the
driver.

[mszyprow: rebased onto v3.18-rc1, added error message when prefetch related
dt property has been provided without any value]

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: 8260/1: l2c: Add interface to ask hypervisor to configure L2C

Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed

ARM: 8260/1: l2c: Add interface to ask hypervisor to configure L2C

Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure the hardware according to
specified parameters. This patch adds such.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: 8259/1: l2c: Refactor the driver to use commit-like interface

Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to indivi

ARM: 8259/1: l2c: Refactor the driver to use commit-like interface

Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.

This patch is first step to make the driver not rely on availability of
writes to individual registers. This is achieved by refactoring the
driver to use a commit-like operation scheme: all register values are
prepared first and stored in an instance of l2x0_regs struct and then a
single callback is responsible to flush those values to the hardware.

[mszyprow: rebased onto 'ARM: l2c: use l2c_write_sec() for restoring
latency and filter regs' patch]

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regs

All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_writ

ARM: 8258/1: l2c: use l2c_write_sec() for restoring latency and filter regs

All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for r3p3, but it should be uniform for all revisions.

Reported-by: Nishanth Menon <nm@ti.com>
Suggested-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: 8183/1: l2c: Improve l2c310_of_parse() error message

Russell King suggested [1]:

"I'd ask for one change. Please make all these messages start with
"L2C-310 OF" not "PL310 OF:". The device i

ARM: 8183/1: l2c: Improve l2c310_of_parse() error message

Russell King suggested [1]:

"I'd ask for one change. Please make all these messages start with
"L2C-310 OF" not "PL310 OF:". The device is described in ARM
documentation as a L2C-310 not PL310. (Also note the : is dropped
too - most of the other messages don't have the : either.)

The:

"PL310 OF: cache setting yield illegal associativity
PL310 OF: -1073346556 calculated, only 8 and 16 legal"

message could also be changed to something like:

"L2C-310 OF cache associativity %d invalid, only 8 or 16 permittedn"

[1] http://www.spinics.net/lists/arm-kernel/msg372776.html

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: 8182/1: l2c: Make l2x0_cache_size_of_parse() return 'int'

Since commit f3354ab67476dc80 ("ARM: 8169/1: l2c: parse cache properties from
ePAPR definitions") the following error is seen on imx6q:

ARM: 8182/1: l2c: Make l2x0_cache_size_of_parse() return 'int'

Since commit f3354ab67476dc80 ("ARM: 8169/1: l2c: parse cache properties from
ePAPR definitions") the following error is seen on imx6q:

[ 0.000000] PL310 OF: cache setting yield illegal associativity
[ 0.000000] PL310 OF: -2147097556 calculated, only 8 and 16 legal

As imx6q does not pass the "cache-size" and "cache-sets" properties in DT, the function l2x0_cache_size_of_parse() returns early and keep the 'associativity' pointer uninitialized.

To fix this problem, return error codes inside l2x0_cache_size_of_parse() and only use the 'associativity' pointer result if l2x0_cache_size_of_parse() succeeds.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: 8169/1: l2c: parse cache properties from ePAPR definitions

When both 'cache-size' and 'cache-sets' are specified for a L2 cache
controller node, parse those properties and set up the
set size b

ARM: 8169/1: l2c: parse cache properties from ePAPR definitions

When both 'cache-size' and 'cache-sets' are specified for a L2 cache
controller node, parse those properties and set up the
set size based on which type of L2 cache controller we are using.

Update the L2 cache controller Device Tree binding with the optional
'cache-size', 'cache-sets', 'cache-block-size' and 'cache-line-size'
properties. These come from the ePAPR specification.

Using the cache size, number of sets and cache line size we can
calculate desired associativity of the L2 cache. This is done
by the calculation:

set size = cache size / sets
ways = set size / line size
way size = cache size / ways = sets * line size
associativity = cache size / way size

Example output from the PB1176 DT that look like this:

L2: l2-cache {
compatible = "arm,l220-cache";
(...)
arm,override-auxreg;
cache-size = <131072>; // 128kB
cache-sets = <512>;
cache-line-size = <32>;
};

Ends up like this:

L2C OF: override cache size: 131072 bytes (128KB)
L2C OF: override line size: 32 bytes
L2C OF: override way size: 16384 bytes (16KB)
L2C OF: override associativity: 8
L2C: DT/platform modifies aux control register: 0x02020fff -> 0x02030fff
L2C-220 cache controller enabled, 8 ways, 128 kB
L2C-220: CACHE_ID 0x41000486, AUX_CTRL 0x06030fff

Which is consistent with the value earlier hardcoded for the
PB1176 platform.

This patch is an extended version based on the initial patch
by Florian Fainelli.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: make it easier to check the CPU part number correctly

Ensure that platform maintainers check the CPU part number in the right
manner: the CPU part number is meaningless without also checking th

ARM: make it easier to check the CPU part number correctly

Ensure that platform maintainers check the CPU part number in the right
manner: the CPU part number is meaningless without also checking the
CPU implement(e|o)r (choose your preferred spelling!) Provide an
interface which returns both the implementer and part number together,
and update the definitions to include the implementer.

Mark the old function as being deprecated... indeed, using the old
function with the definitions will now always evaluate as false, so
people must update their un-merged code to the new function. While
this could be avoided by adding new definitions, we'd also have to
create new names for them which would be awkward.

Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: fix revision checking

The revision checking in l2c310_enable() was not correct; we were
masking the part number rather than the revision number. Fix this
to use the correct macro.

Fixes:

ARM: l2c: fix revision checking

The revision checking in l2c310_enable() was not correct; we were
masking the part number rather than the revision number. Fix this
to use the correct macro.

Fixes: 4374d64933b1 ("ARM: l2c: add automatic enable of early BRESP")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache

When a PL310 cache is used on a system that provides hardware
coherency, the outer cache sync operation is useless, and can be
ski

ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache

When a PL310 cache is used on a system that provides hardware
coherency, the outer cache sync operation is useless, and can be
skipped. Moreover, on some systems, it is harmful as it causes
deadlocks between the Marvell coherency mechanism, the Marvell PCIe
controller and the Cortex-A9.

To avoid this, this commit introduces a new Device Tree property
'arm,io-coherent' for the L2 cache controller node, valid only for the
PL310 cache. It identifies the usage of the PL310 cache in an I/O
coherent configuration. Internally, it makes the driver disable the
outer cache sync operation.

Note that technically speaking, a fully coherent system wouldn't
require any of the other .outer_cache operations. However, in
practice, when booting secondary CPUs, these are not yet coherent, and
therefore a set of cache maintenance operations are necessary at this
point. This explains why we keep the other .outer_cache operations and
only ->sync is disabled.

While in theory any write to a PL310 register could cause the
deadlock, in practice, disabling ->sync is sufficient to workaround
the deadlock, since the other cache maintenance operations are only
used in very specific situations.

Contrary to previous versions of this patch, this new version does not
simply NULL-ify the ->sync member, because the l2c_init_data
structures are now 'const' and therefore cannot be modified, which is
a good thing. Therefore, this patch introduces a separate
l2c_init_data instance, called of_l2c310_coherent_data.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: trial at enabling some Cortex-A9 optimisations

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: l2c: add warnings for stuff modifying aux_ctrl register values

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: l2c: print a warning with L2C-310 caches if the cache size is modified

As we have now removed all instances of the L2C-310 having its cache
size "modified" via platform/SoC code, discourage new

ARM: l2c: print a warning with L2C-310 caches if the cache size is modified

As we have now removed all instances of the L2C-310 having its cache
size "modified" via platform/SoC code, discourage new cases showing
up by printing a warning.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: remove old .set_debug method

We no longer need or require the .set_debug method; we handle everything
it used to do via the .write_sec method instead.

Signed-off-by: Russell King <rmk+ker

ARM: l2c: remove old .set_debug method

We no longer need or require the .set_debug method; we handle everything
it used to do via the .write_sec method instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: always enable non-secure access to lockdown registers

Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set. Set i

ARM: l2c: always enable non-secure access to lockdown registers

Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set. Set it in
core code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: always enable low power modes

Always enable the L2C low power modes on L2C-310 R3P0 and newer parts.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: l2c: add automatic enable of early BRESP

The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted. Early
BRESP allows th

ARM: l2c: add automatic enable of early BRESP

The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted. Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.

Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: move L2 cache register saving to a more sensible location

Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run. We mo

ARM: l2c: move L2 cache register saving to a more sensible location

Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run. We move the
saving of the auxiliary control register into the ->save function as
well which makes everything operate in a sane and maintainable way.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: check that DT files specify the required "cache-unified" property

This is a required property, and should always be specified.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: l2c: fix register naming

We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-3

ARM: l2c: fix register naming

We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices. Provide full auxiliary control register definitions.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: implement L2C-310 erratum 752271 in core L2C code

Rather than having SoCs work around L2C erratum themselves, move them
into core code. This erratum affects the double linefill feature wh

ARM: l2c: implement L2C-310 erratum 752271 in core L2C code

Rather than having SoCs work around L2C erratum themselves, move them
into core code. This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: provide generic hook to intercept writes to secure registers

When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort. Platforms normally h

ARM: l2c: provide generic hook to intercept writes to secure registers

When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort. Platforms normally have to call
firmware to work around this. Provide a hook for them to intercept
any L2C secure register write.

l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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