ARM: qcom: Fix SCM interface for big-endian kernels

The secure environment only runs in little-endian mode, so any
buffers shared with the secure environment should have their
contents converted to

ARM: qcom: Fix SCM interface for big-endian kernels

The secure environment only runs in little-endian mode, so any
buffers shared with the secure environment should have their
contents converted to little-endian. We also mark such elements
with __le32 to allow sparse to catch such problems.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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ARM: qcom: scm: Clarify boot interface

The secure world only knows about 32-bit wide physical addresses
for the boot API. Clarify the kernel interface by explicitly
stating a u32 instead of phys_add

ARM: qcom: scm: Clarify boot interface

The secure world only knows about 32-bit wide physical addresses
for the boot API. Clarify the kernel interface by explicitly
stating a u32 instead of phys_addr_t which could be 32 or 64 bits
depending on LPAE or not.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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ARM: qcom: Add SCM warmboot flags for quad core targets.

Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
s

ARM: qcom: Add SCM warmboot flags for quad core targets.

Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warmboot addresses for secondary cores.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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ARM: qcom: scm: Add logging of actual return code from scm call

When an error occurs during an scm call the error returned is remapped so
we lose the original error code. This means that when an err

ARM: qcom: scm: Add logging of actual return code from scm call

When an error occurs during an scm call the error returned is remapped so
we lose the original error code. This means that when an error occurs we
have no idea what actually failed within the secure environment.

Add a logging statement that will log the actual error code from scm call
allowing us to easily determine what caused the error to occur.

Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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ARM: qcom: scm: Flush the command buffer only instead of the entire cache

scm_call flushes the entire cache before calling into the secure world.
This is both a performance penalty as well as insuff

ARM: qcom: scm: Flush the command buffer only instead of the entire cache

scm_call flushes the entire cache before calling into the secure world.
This is both a performance penalty as well as insufficient on SMP systems
where the CPUs possess a write-back L1 cache. Flush only the command and
response buffers instead, moving the responsibility of flushing any other
cached buffer (being passed to the secure world) to callers.

Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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ARM: qcom: scm: Get cacheline size from CTR

Instead of hardcoding the cacheline size as 32, get the cacheline size from
the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-o

ARM: qcom: scm: Get cacheline size from CTR

Instead of hardcoding the cacheline size as 32, get the cacheline size from
the CTR register.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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ARM: qcom: scm: Fix incorrect cache invalidation

The cache invalidation in scm_call() correctly rounds down the start
address to invalidate the beginning of the cacheline but doesn't properly
round

ARM: qcom: scm: Fix incorrect cache invalidation

The cache invalidation in scm_call() correctly rounds down the start
address to invalidate the beginning of the cacheline but doesn't properly
round up the 'end' address to make it aligned. The last chunk of the
buffer won't be invalidated when 'end' is not cacheline size aligned so
make sure to invalidate the last few bytes in such situations. It also
doesn't do anything about outer caches so make sure to invalidate and flush
those as well.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIAN

We can run qcom platforms in big-endian mode. Select the option.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codea

ARM: qcom: Select ARCH_SUPPORTS_BIG_ENDIAN

We can run qcom platforms in big-endian mode. Select the option.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

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