Revision tags: v3.10-rc7 |
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#
18d7f152 |
| 19-Jun-2013 |
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
ARM: 7763/1: kernel: fix __cpu_logical_map default initialization
The __cpu_logical_map array is statically initialized to 0, which is a valid MPIDR value. To prevent issues with the current impleme
ARM: 7763/1: kernel: fix __cpu_logical_map default initialization
The __cpu_logical_map array is statically initialized to 0, which is a valid MPIDR value. To prevent issues with the current implementation, this patch defines an MPIDR_INVALID value, and statically initializes the __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps() tmp_map array used to stash DT reg properties while parsing DT are initialized with the MPIDR_INVALID value as well for consistency.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Revision tags: v3.10-rc6, v3.10-rc5, v3.10-rc4, v3.10-rc3, v3.10-rc2 |
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#
8cf72172 |
| 16-May-2013 |
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
ARM: kernel: build MPIDR hash function data structure
On ARM SMP systems, cores are identified by their MPIDR register. The MPIDR guidelines in the ARM ARM do not provide strict enforcement of MPIDR
ARM: kernel: build MPIDR hash function data structure
On ARM SMP systems, cores are identified by their MPIDR register. The MPIDR guidelines in the ARM ARM do not provide strict enforcement of MPIDR layout, only recommendations that, if followed, split the MPIDR on ARM 32 bit platforms in three affinity levels. In multi-cluster systems like big.LITTLE, if the affinity guidelines are followed, the MPIDR can not be considered an index anymore. This means that the association between logical CPU in the kernel and the HW CPU identifier becomes somewhat more complicated requiring methods like hashing to associate a given MPIDR to a CPU logical index, in order for the look-up to be carried out in an efficient and scalable way.
This patch provides a function in the kernel that starting from the cpu_logical_map, implement collision-free hashing of MPIDR values by checking all significative bits of MPIDR affinity level bitfields. The hashing can then be carried out through bits shifting and ORing; the resulting hash algorithm is a collision-free though not minimal hash that can be executed with few assembly instructions. The mpidr is filtered through a mpidr mask that is built by checking all bits that toggle in the set of MPIDRs corresponding to possible CPUs. Bits that do not toggle do not carry information so they do not contribute to the resulting hash.
Pseudo code:
/* check all bits that toggle, so they are required */ for (i = 1, mpidr_mask = 0; i < num_possible_cpus(); i++) mpidr_mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
/* * Build shifts to be applied to aff0, aff1, aff2 values to hash the mpidr * fls() returns the last bit set in a word, 0 if none * ffs() returns the first bit set in a word, 0 if none */ fs0 = mpidr_mask[7:0] ? ffs(mpidr_mask[7:0]) - 1 : 0; fs1 = mpidr_mask[15:8] ? ffs(mpidr_mask[15:8]) - 1 : 0; fs2 = mpidr_mask[23:16] ? ffs(mpidr_mask[23:16]) - 1 : 0; ls0 = fls(mpidr_mask[7:0]); ls1 = fls(mpidr_mask[15:8]); ls2 = fls(mpidr_mask[23:16]); bits0 = ls0 - fs0; bits1 = ls1 - fs1; bits2 = ls2 - fs2; aff0_shift = fs0; aff1_shift = 8 + fs1 - bits0; aff2_shift = 16 + fs2 - (bits0 + bits1); u32 hash(u32 mpidr) { u32 l0, l1, l2; u32 mpidr_masked = mpidr & mpidr_mask; l0 = mpidr_masked & 0xff; l1 = mpidr_masked & 0xff00; l2 = mpidr_masked & 0xff0000; return (l0 >> aff0_shift | l1 >> aff1_shift | l2 >> aff2_shift); }
The hashing algorithm relies on the inherent properties set in the ARM ARM recommendations for the MPIDR. Exotic configurations, where for instance the MPIDR values at a given affinity level have large holes, can end up requiring big hash tables since the compression of values that can be achieved through shifting is somewhat crippled when holes are present. Kernel warns if the number of buckets of the resulting hash table exceeds the number of possible CPUs by a factor of 4, which is a symptom of a very sparse HW MPIDR configuration.
The hash algorithm is quite simple and can easily be implemented in assembly code, to be used in code paths where the kernel virtual address space is not set-up (ie cpu_resume) and instruction and data fetches are strongly ordered so code must be compact and must carry out few data accesses.
Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Colin Cross <ccross@android.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
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Revision tags: v3.10-rc1, v3.9, v3.9-rc8, v3.9-rc7 |
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#
a469abd0 |
| 08-Apr-2013 |
Will Deacon <will.deacon@arm.com> |
ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions
CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that userspace software can avoid having to use the exclusive
ARM: elf: add new hwcap for identifying atomic ldrd/strd instructions
CPUs implementing LPAE have atomic ldrd/strd instructions, meaning that userspace software can avoid having to use the exclusive variants of these instructions if they wish.
This patch advertises the atomicity of these instructions via the hwcaps, so userspace can detect this CPU feature.
Reported-by: Vladimir Danushevsky <vladimir.danushevsky@oracle.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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#
b382b940 |
| 21-May-2013 |
Jon Medhurst <tixy@linaro.org> |
ARM: Enable selection of SMP operations at boot time
Add a new 'smp_init' hook to machine_desc so platforms can specify a function to be used to setup smp ops instead of having a statically defined
ARM: Enable selection of SMP operations at boot time
Add a new 'smp_init' hook to machine_desc so platforms can specify a function to be used to setup smp ops instead of having a statically defined value. The hook must return true when smp_ops are initialized. If false the static mdesc->smp_ops will be used by default.
Add the definition of "bool" by including the linux/types.h file to asm/mach/arch.h and make it self-contained.
Signed-off-by: Jon Medhurst <tixy@linaro.org> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
05774088 |
| 21-May-2013 |
Stefano Stabellini <stefano.stabellini@eu.citrix.com> |
arm: introduce psci_smp_ops
Rename virt_smp_ops to psci_smp_ops and move them to arch/arm/kernel/psci_smp.c. Remove mach-virt/platsmp.c, now unused. Compile psci_smp if CONFIG_ARM_PSCI and CONFIG_SM
arm: introduce psci_smp_ops
Rename virt_smp_ops to psci_smp_ops and move them to arch/arm/kernel/psci_smp.c. Remove mach-virt/platsmp.c, now unused. Compile psci_smp if CONFIG_ARM_PSCI and CONFIG_SMP.
Add a cpu_die smp_op based on psci_ops.cpu_off.
Initialize PSCI before setting smp_ops in setup_arch.
If PSCI is available on the platform, prefer psci_smp_ops over the platform smp_ops.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Will Deacon <will.deacon@arm.com> CC: arnd@arndb.de CC: marc.zyngier@arm.com CC: linux@arm.linux.org.uk CC: nico@linaro.org CC: rob.herring@calxeda.com
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Revision tags: v3.9-rc6, v3.9-rc5, v3.9-rc4, v3.9-rc3 |
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#
9394c1c6 |
| 11-Mar-2013 |
Ming Lei <tom.leiming@gmail.com> |
ARM: 7669/1: keep __my_cpu_offset consistent with generic one
Commit 14318efb(ARM: 7587/1: implement optimized percpu variable access) introduces arm's __my_cpu_offset to optimize percpu vaiable acc
ARM: 7669/1: keep __my_cpu_offset consistent with generic one
Commit 14318efb(ARM: 7587/1: implement optimized percpu variable access) introduces arm's __my_cpu_offset to optimize percpu vaiable access, which really works well on hackbench, but will cause __my_cpu_offset to return garbage value before it is initialized in cpu_init() called by setup_arch, so accessing percpu variable before setup_arch may cause kernel hang. But generic __my_cpu_offset always returns zero before percpu area is brought up, and won't hang kernel.
So the patch tries to clear __my_cpu_offset on boot CPU early to avoid boot hang.
At least now percpu variable is accessed by lockdep before setup_arch(), and enabling CONFIG_LOCK_STAT or CONFIG_DEBUG_LOCKDEP can trigger kernel hang.
Signed-off-by: Ming Lei <tom.leiming@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Revision tags: v3.9-rc2, v3.9-rc1, v3.8, v3.8-rc7, v3.8-rc6 |
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#
883a106b |
| 31-Jan-2013 |
Arnd Bergmann <arnd@arndb.de> |
ARM: default machine descriptor for multiplatform
Since we now have default implementations for init_time and init_irq, the init_machine callback is the only one that is not yet optional, but since
ARM: default machine descriptor for multiplatform
Since we now have default implementations for init_time and init_irq, the init_machine callback is the only one that is not yet optional, but since simple DT based platforms all have the same of_platform_populate function call in there, we can consolidate them as well, and then actually boot with a completely empty machine_desc. Unofortunately we cannot just default to an empty init_machine: We cannot call of_platform_populate before init_machine because that does not work in case of auxdata, and we cannot call it after init_machine either because the machine might need to run code after adding the devices.
To take the final step, this adds support for booting without defining any machine_desc whatsoever.
For the case that CONFIG_MULTIPLATFORM is enabled, it adds a global machine descriptor that never matches any machine but is used as a fallback if nothing else matches. We assume that without CONFIG_MULTIPLATFORM, we only want to boot on the systems that the kernel is built for, so we still retain the build-time warning for missing machine descriptors and the run-time warning when the platform does not match in that case.
In the case that we run on a multiplatform kernel and the machine provides a fully populated device tree, we attempt to keep booting, hoping that no machine specific callbacks are necessary.
Finally, this also removes the misguided "select ARCH_VEXPRESS" that was only added to avoid a build error for allnoconfig kernels.
Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Cc: "Russell King - ARM Linux" <linux@arm.linux.org.uk> Cc: Rob Herring <robherring2@gmail.com>
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#
1783d457 |
| 25-Apr-2013 |
Jon Medhurst <tixy@linaro.org> |
ARM: 7700/2: Make cpu_init() notrace
On resume from CPU power down any trace hooks enabled in cpu_init() will get called before that function has done set_my_cpu_offset(), so any use of per-cpu vari
ARM: 7700/2: Make cpu_init() notrace
On resume from CPU power down any trace hooks enabled in cpu_init() will get called before that function has done set_my_cpu_offset(), so any use of per-cpu variables by trace hook code will cause bad things to happen. Prevent this by marking the function notrace.
This fixes lockups/crashes seen when enabling function tracer on TC2 with the not yet mainlined cpuidle driver.
Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Revision tags: v3.8-rc5, v3.8-rc4, v3.8-rc3, v3.8-rc2, v3.8-rc1, v3.7, v3.7-rc8, v3.7-rc7, v3.7-rc6, v3.7-rc5, v3.7-rc4, v3.7-rc3, v3.7-rc2, v3.7-rc1, v3.6, v3.6-rc7, v3.6-rc6, v3.6-rc5, v3.6-rc4, v3.6-rc3, v3.6-rc2, v3.6-rc1, v3.5, v3.5-rc7, v3.5-rc6, v3.5-rc5, v3.5-rc4, v3.5-rc3, v3.5-rc2, v3.5-rc1, v3.4, v3.4-rc7, v3.4-rc6, v3.4-rc5, v3.4-rc4, v3.4-rc3, v3.4-rc2, v3.4-rc1, v3.3, v3.3-rc7, v3.3-rc6, v3.3-rc5, v3.3-rc4, v3.3-rc3, v3.3-rc2, v3.3-rc1, v3.2, v3.2-rc7, v3.2-rc6, v3.2-rc5, v3.2-rc4, v3.2-rc3, v3.2-rc2, v3.2-rc1, v3.1, v3.1-rc10, v3.1-rc9, v3.1-rc8, v3.1-rc7, v3.1-rc6, v3.1-rc5, v3.1-rc4, v3.1-rc3, v3.1-rc2, v3.1-rc1, v3.0, v3.0-rc7, v3.0-rc6, v3.0-rc5, v3.0-rc4, v3.0-rc3, v3.0-rc2, v3.0-rc1, v2.6.39, v2.6.39-rc7, v2.6.39-rc6, v2.6.39-rc5, v2.6.39-rc4, v2.6.39-rc3, v2.6.39-rc2, v2.6.39-rc1, v2.6.38, v2.6.38-rc8, v2.6.38-rc7, v2.6.38-rc6, v2.6.38-rc5, v2.6.38-rc4, v2.6.38-rc3, v2.6.38-rc2, v2.6.38-rc1, v2.6.37, v2.6.37-rc8, v2.6.37-rc7, v2.6.37-rc6, v2.6.37-rc5, v2.6.37-rc4, v2.6.37-rc3, v2.6.37-rc2, v2.6.37-rc1, v2.6.36, v2.6.36-rc8, v2.6.36-rc7, v2.6.36-rc6, v2.6.36-rc5, v2.6.36-rc4, v2.6.36-rc3, v2.6.36-rc2, v2.6.36-rc1, v2.6.35, v2.6.35-rc6, v2.6.35-rc5, v2.6.35-rc4, v2.6.35-rc3, v2.6.35-rc2, v2.6.35-rc1 |
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#
55bdd694 |
| 21-May-2010 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: Add base support for ARMv7-M
This patch adds the base support for the ARMv7-M architecture. It consists of the corresponding arch/arm/mm/ files and various #ifdef's around the kernel. Exception
ARM: Add base support for ARMv7-M
This patch adds the base support for the ARMv7-M architecture. It consists of the corresponding arch/arm/mm/ files and various #ifdef's around the kernel. Exception handling is implemented by a subsequent patch.
[ukleinek: squash in some changes originating from commit
b5717ba (Cortex-M3: Add support for the Microcontroller Prototyping System)
from the v2.6.33-arm1 patch stack, port to post 3.6, drop zImage support, drop reorganisation of pt_regs, assert CONFIG_CPU_V7M doesn't leak into installed headers and a few cosmetic changes]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Jonathan Austin <jonathan.austin@arm.com> Tested-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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#
de40614e |
| 04-Apr-2013 |
Joonsoo Kim <iamjoonsoo.kim@lge.com> |
ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch()
tcm_init() call iotable_init() and it use early_alloc variants which do memblock allocation. Directly using memblock a
ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch()
tcm_init() call iotable_init() and it use early_alloc variants which do memblock allocation. Directly using memblock allocation after initializing bootmem should not permitted, because bootmem can't know where are additinally reserved. So move tcm_init() to a safe place before initalizing bootmem.
(On the U300)
Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
4e1db26a |
| 03-Apr-2013 |
Paul Bolle <pebolle@tiscali.nl> |
ARM: 7690/1: mm: fix CONFIG_LPAE typos
CONFIG_LPAE doesn't exist: the correct option is CONFIG_ARM_LPAE, so fix up the two typos under arch/arm/.
The fix to head.S is slightly scary, but this is ju
ARM: 7690/1: mm: fix CONFIG_LPAE typos
CONFIG_LPAE doesn't exist: the correct option is CONFIG_ARM_LPAE, so fix up the two typos under arch/arm/.
The fix to head.S is slightly scary, but this is just for setting up an early io-mapping for the serial port when running on a big-endian, LPAE system. Since these systems don't exist in the wild (at least, I have no access to one outside of kvmtool, which doesn't provide a serial port suitable for earlyprintk), then we can revisit the code later if it causes any problems.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
8164f7af |
| 18-Mar-2013 |
Stephen Boyd <sboyd@codeaurora.org> |
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register
The ISAR0 register indicates support for the SDIV and UDIV instructions in both the Thumb and ARM instruction set. Read the register to
ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register
The ISAR0 register indicates support for the SDIV and UDIV instructions in both the Thumb and ARM instruction set. Read the register to detect the supported instructions and update the elf_hwcap mask as appropriate. This is better than adding more and more cpuid checks in proc-v7.S for each new cpu variant that supports these instructions.
Acked-by: Will Deacon <will.deacon@arm.com> Cc: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
c40e3641 |
| 18-Mar-2013 |
Stephen Boyd <sboyd@codeaurora.org> |
ARM: 7679/1: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n
Don't advertise support for the SDIV/UDIV thumb instructions if the kernel is not compiled with support for thumb userspace. This is in line with
ARM: 7679/1: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n
Don't advertise support for the SDIV/UDIV thumb instructions if the kernel is not compiled with support for thumb userspace. This is in line with how we remove the THUMB hwcap in these configurations.
Acked-by: Will Deacon <will.deacon@arm.com> Cc: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
ac52e83f |
| 30-Jan-2013 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
ARM: use read_cpuid_id() instead of read_cpuid(CPUID_ID)
Both calls are identical currently. This patch prepares to deprecate read_cpuid on machines without cp15.
Also move an unconditional usage o
ARM: use read_cpuid_id() instead of read_cpuid(CPUID_ID)
Both calls are identical currently. This patch prepares to deprecate read_cpuid on machines without cp15.
Also move an unconditional usage of read_cpuid_cachetype to a more local scope as read_cpuid_cachetype uses read_cpuid, too.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Message-Id: 1359646587-1788-1-git-send-email-u.kleine-koenig@pengutronix.de
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#
b8b499c8 |
| 12-Dec-2012 |
Alexander Shiyan <shc_work@mail.ru> |
ARM: 7602/1: Pass real "__machine_arch_type" variable to setup_machine_tags() procedure
This modification is needed to proper boot the custom machines with the IDs that are not described in the mach
ARM: 7602/1: Pass real "__machine_arch_type" variable to setup_machine_tags() procedure
This modification is needed to proper boot the custom machines with the IDs that are not described in the mach-types.h table.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
14318efb |
| 29-Nov-2012 |
Rob Herring <rob.herring@calxeda.com> |
ARM: 7587/1: implement optimized percpu variable access
Use the previously unused TPIDRPRW register to store percpu offsets. TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.
ARM: 7587/1: implement optimized percpu variable access
Use the previously unused TPIDRPRW register to store percpu offsets. TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.
This replaces 2 loads with a mrc instruction for each percpu variable access. With hackbench, the performance improvement is 1.4% on Cortex-A9 (highbank). Taking an average of 30 runs of "hackbench -l 1000" yields:
Before: 6.2191 After: 6.1348
Will Deacon reported similar delta on v6 with 11MPCore.
The asm "memory clobber" are needed here to ensure the percpu offset gets reloaded. Testing by Will found that this would not happen in __schedule() which is a bit of a special case as preemption is disabled but the execution can move cores.
Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
5587164e |
| 14-Dec-2011 |
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
ARM: kernel: add cpu logical map DT init in setup_arch
As soon as the device tree is unflattened the cpu logical to physical mapping is carried out in setup_arch to build a proper array of MPIDR and
ARM: kernel: add cpu logical map DT init in setup_arch
As soon as the device tree is unflattened the cpu logical to physical mapping is carried out in setup_arch to build a proper array of MPIDR and corresponding logical indexes.
The mapping could have been carried out using the flattened DT blob and related primitives, but since the mapping is not needed by early boot code it can safely be executed when the device tree has been uncompressed to its tree data structure.
This patch adds the arm_dt_init_cpu maps() function call in setup_arch().
If the kernel is not compiled with DT support the function is empty and no logical mapping takes place through it; the mapping carried out in smp_setup_processor_id() is left unchanged. If DT is supported the mapping created in smp_setup_processor_id() is overriden. The DT mapping also sets the possible cpus mask, hence platform code need not set it again in the respective smp_init_cpus() functions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org>
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#
cb8cf4f8 |
| 08-Nov-2012 |
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
ARM: kernel: smp_setup_processor_id() updates
This patch applies some basic changes to the smp_setup_processor_id() ARM implementation to make the code that builds cpu_logical_map more uniform acros
ARM: kernel: smp_setup_processor_id() updates
This patch applies some basic changes to the smp_setup_processor_id() ARM implementation to make the code that builds cpu_logical_map more uniform across the kernel.
The function now prints the full extent of the boot CPU MPIDR[23:0] and initializes the cpu_logical_map for CPUs up to nr_cpu_ids.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com>
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#
b4b8f770 |
| 10-Sep-2012 |
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
ARM: kernel: update cpuinfo to print all online CPUs features
Currently, reading /proc/cpuinfo provides userspace with CPU ID of the CPU carrying out the read from the file. This is fine as long as
ARM: kernel: update cpuinfo to print all online CPUs features
Currently, reading /proc/cpuinfo provides userspace with CPU ID of the CPU carrying out the read from the file. This is fine as long as all CPUs in the system are the same. With the advent of big.LITTLE and heterogenous ARM systems this approach provides user space with incorrect bits of information since CPU ids in the system might differ from the one provided by the CPU reading the file.
This patch updates the cpuinfo show function so that a read from /proc/cpuinfo prints HW information for all online CPUs at once, mirroring x86 behaviour.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org>
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#
4588c34d |
| 17-Feb-2012 |
Dave Martin <dave.martin@linaro.org> |
ARM: virt: Add boot-time diagnostics
In order to easily detect pathological cases, print some diagnostics when the kernel boots.
This also provides helpers to detect that HYP mode is actually avail
ARM: virt: Add boot-time diagnostics
In order to easily detect pathological cases, print some diagnostics when the kernel boots.
This also provides helpers to detect that HYP mode is actually available, which can be used by other subsystems to enable HYP specific features.
Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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abcee5fb |
| 08-Sep-2011 |
Marc Zyngier <marc.zyngier@arm.com> |
ARM: SoC: add per-platform SMP operations
This adds a 'struct smp_operations' to abstract the CPU initialization and hot plugging functions on SMP systems, which otherwise conflict in a multiplatfor
ARM: SoC: add per-platform SMP operations
This adds a 'struct smp_operations' to abstract the CPU initialization and hot plugging functions on SMP systems, which otherwise conflict in a multiplatform kernel. This also helps shmobile and potentially others that have more than one method to do these.
To allow the kernel to continue building, the platform hooks are defined as weak symbols which are overrided by the platform code. Once all platforms are converted, the "weak" attribute will be removed and the function made static.
Unlike the original version from Marc, this new version from Arnd does not use a generalized abstraction for per-soc data structures but only tries to solve the problem for the SMP operations. This way, we can collapse the previous four data structures into a single struct, which is less systematic but also easier to follow as a causal reader.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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aa783b6f |
| 31-Aug-2012 |
Nicolas Pitre <nicolas.pitre@linaro.org> |
ARM: 7505/1: split out ATAGS parsing
Make ATAGS parsing into a source file of its own, namely atags_parse.c. Also rename compat.c to atags_compat.c to make it clearer what it is about. Same for ata
ARM: 7505/1: split out ATAGS parsing
Make ATAGS parsing into a source file of its own, namely atags_parse.c. Also rename compat.c to atags_compat.c to make it clearer what it is about. Same for atags.c which is now atags_proc.c. Gather all the atags function declarations into a common atags.h.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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a5d5f7da |
| 12-Jul-2012 |
Peter Maydell <peter.maydell@linaro.org> |
ARM: 7465/1: Handle >4GB memory sizes in device tree and mem=size@start option
The memory regions which are passed to arm_add_memory() from device tree blobs via early_init_dt_add_memory_arch() can
ARM: 7465/1: Handle >4GB memory sizes in device tree and mem=size@start option
The memory regions which are passed to arm_add_memory() from device tree blobs via early_init_dt_add_memory_arch() can have sizes which are larger than will fit in a 32 bit integer, so switch to using a phys_addr_t to hold them, to avoid silently dropping the top 32 bits of the size. Similarly, use phys_addr_t in early_mem() so that mem=size@start command line options specifying more than 4GB behave sensibly.
Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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c7909509 |
| 29-Dec-2011 |
Marek Szyprowski <m.szyprowski@samsung.com> |
ARM: integrate CMA with DMA-mapping subsystem
This patch adds support for CMA to dma-mapping subsystem for ARM architecture. By default a global CMA area is used, but specific devices are allowed to
ARM: integrate CMA with DMA-mapping subsystem
This patch adds support for CMA to dma-mapping subsystem for ARM architecture. By default a global CMA area is used, but specific devices are allowed to have their private memory areas if required (they can be created with dma_declare_contiguous() function during board initialisation).
Contiguous memory areas reserved for DMA are remapped with 2-level page tables on boot. Once a buffer is requested, a low memory kernel mapping is updated to to match requested memory access type.
GFP_ATOMIC allocations are performed from special pool which is created early during boot. This way remapping page attributes is not needed on allocation time.
CMA has been enabled unconditionally for ARMv6+ systems.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Michal Nazarewicz <mina86@mina86.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Rob Clark <rob.clark@linaro.org> Tested-by: Ohad Ben-Cohen <ohad@wizery.com> Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Tested-by: Robert Nelson <robertcnelson@gmail.com> Tested-by: Barry Song <Baohua.Song@csr.com>
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90de4137 |
| 25-Apr-2012 |
Shawn Guo <shawn.guo@linaro.org> |
ARM: provide a late_initcall hook for platform initialization
This allows platforms to set up things that need to be done at late_initcall time.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Test
ARM: provide a late_initcall hook for platform initialization
This allows platforms to set up things that need to be done at late_initcall time.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Robert Lee <rob.lee@linaro.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
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