ARM: efistub: replace adrl pseudo-op with adr_l macro invocation

commit 67e3f828bd4bf5e4eb4214dc4eb227d8f1c8a877 upstream.

The ARM 'adrl' pseudo instruction is a bit problematic, as

ARM: efistub: replace adrl pseudo-op with adr_l macro invocation

commit 67e3f828bd4bf5e4eb4214dc4eb227d8f1c8a877 upstream.

The ARM 'adrl' pseudo instruction is a bit problematic, as it does not
exist in Thumb mode, and it is not implemented by Clang either. Since
the Thumb variant has a slightly bigger range, it is sometimes necessary
to emit the 'adrl' variant in ARM mode where Thumb mode can use adr just
fine. However, that still leaves the Clang issue, which does not appear
to be supporting this any time soon.

So let's switch to the adr_l macro, which works for both ARM and Thumb,
and has unlimited range.

Reviewed-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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ARM: 9046/1: decompressor: Do not clear SCTLR.nTLSMD for ARMv7+ cores

[ Upstream commit 2acb909750431030b65a0a2a17fd8afcbd813a84 ]

It was observed that decompressor running on hardw

ARM: 9046/1: decompressor: Do not clear SCTLR.nTLSMD for ARMv7+ cores

[ Upstream commit 2acb909750431030b65a0a2a17fd8afcbd813a84 ]

It was observed that decompressor running on hardware implementing ARM v8.2
Load/Store Multiple Atomicity and Ordering Control (LSMAOC), say, as guest,
would stuck just after:

Uncompressing Linux... done, booting the kernel.

The reason is that it clears nTLSMD bit when disabling caches:

nTLSMD, bit [3]

When ARMv8.2-LSMAOC is implemented:

No Trap Load Multiple and Store Multiple to
Device-nGRE/Device-nGnRE/Device-nGnRnE memory.

0b0 All memory accesses by A32 and T32 Load Multiple and Store
Multiple at EL1 or EL0 that are marked at stage 1 as
Device-nGRE/Device-nGnRE/Device-nGnRnE memory are trapped and
generate a stage 1 Alignment fault.

0b1 All memory accesses by A32 and T32 Load Multiple and Store
Multiple at EL1 or EL0 that are marked at stage 1 as
Device-nGRE/Device-nGnRE/Device-nGnRnE memory are not trapped.

This bit is permitted to be cached in a TLB.

This field resets to 1.

Otherwise:

Reserved, RES1

So as effect we start getting traps we are not quite ready for.

Looking into history it seems that mask used for SCTLR clear came from
the similar code for ARMv4, where bit[3] is the enable/disable bit for
the write buffer. That not applicable to ARMv7 and onwards, so retire
that bit from the masks.

Fixes: 7d09e85448dfa78e3e58186c934449aaf6d49b50 ("[ARM] 4393/2: ARMv7: Add uncompressing code for the new CPU Id format")
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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ARM: 9036/1: uncompress: Fix dbgadtb size parameter name

[ Upstream commit 1ecec38547d415054fdb63a231234f44396b6d06 ]

The dbgadtb macro is passed the size of the appended DTB, not t

ARM: 9036/1: uncompress: Fix dbgadtb size parameter name

[ Upstream commit 1ecec38547d415054fdb63a231234f44396b6d06 ]

The dbgadtb macro is passed the size of the appended DTB, not the end
address.

Fixes: c03e41470e901123 ("ARM: 9010/1: uncompress: Print the location of appended DTB")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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efi/arm: set HSCTLR Thumb2 bit correctly for HVC calls from HYP

Commit

db227c19e68db353 ("ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully")

updated the

efi/arm: set HSCTLR Thumb2 bit correctly for HVC calls from HYP

Commit

db227c19e68db353 ("ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully")

updated the EFI entry code to permit firmware to invoke the EFI stub
loader in HYP mode, with the MMU either enabled or disabled, neither
of which is permitted by the EFI spec, but which does happen in the
field.

In the MMU on case, we remain in HYP mode as configured by the firmware,
and rely on the fact that any HVC instruction issued in this mode will
be dispatched via the SVC slot in the HYP vector table. However, this
slot will point to a Thumb2 symbol if the kernel is built in Thumb2
mode, and so we have to configure HSCTLR to ensure that the exception
handlers are invoked in Thumb2 mode as well.

Fixes: db227c19e68db353 ("ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully")
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

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ARM: add malloc size to decompressor kexec size structure

Add the required malloc size to the decompressor kexec size structure.

Signed-off-by: Russell King <rmk+kernel@armlinux.org

ARM: add malloc size to decompressor kexec size structure

Add the required malloc size to the decompressor kexec size structure.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: 9010/1: uncompress: Print the location of appended DTB

When using the kernel with an appended DTB it is useful to
know where this will end up in the physical memory at the
time

ARM: 9010/1: uncompress: Print the location of appended DTB

When using the kernel with an appended DTB it is useful to
know where this will end up in the physical memory at the
time the kernel boots.

We add a debug print macro that will help out with this.
Here is a sample debug print after passing -DDEBUG to head.S
during compilation:

DTB:0x40CEBA70 (0x000051B5)
C:0x402080C0-0x40CF0CE0->0x41801D00-0x422EA920
DTB:0x422E56B0 (0x00005262)

This means that the appended DTB is first found after the
compressed kernel at 0x40CEBA70 of size 0x51B5 and then
after the compressed kernel is moved to 0x41801D00
it is found again at 0x422E56B0 and is there size 0x5262.

The growth in size of the FDT is due to the call to
atags_to_fdt() that augments the DTB with ATAG information.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: 9008/1: uncompress: Drop excess whitespace print

This drops some whitespace from the debug message about
where we move the compressed kernel: r after the message
is completely s

ARM: 9008/1: uncompress: Drop excess whitespace print

This drops some whitespace from the debug message about
where we move the compressed kernel: r after the message
is completely surplus since the putc routine will anyway
add r after n, and the initial linefeed just assumes
that this will always be the first message on the console,
which is not certain to be true.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: 9006/1: uncompress: Wait for ready and busy in debug prints

For some platforms such as Qualcomm we need to wait for the
UART to be ready before writing characters to the UART
in

ARM: 9006/1: uncompress: Wait for ready and busy in debug prints

For some platforms such as Qualcomm we need to wait for the
UART to be ready before writing characters to the UART
in the same manner as the macro in debug.S used with the
main "Uncompressing Linux ..." text. Pass an extra temporary
variable to writeb and make it call waituarttxrdy and
busyuart just like the other decomression messages.

Optionally it will also call waituartcts if and only if
CONFIG_DEBUG_UART_FLOW_CONTROL is selected.

After this the decompression debug messages work fine on
Qualcomm platforms if you compile head.S with -DDEBUG.

Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: 9003/1: uncompress: Delete unused debug macros

The debug macros debug_reloc_start and debug_reloc_end were
rendered unused in commit 6d7d0ae51574943bf571d269da3243257a2d15db
"AR

ARM: 9003/1: uncompress: Delete unused debug macros

The debug macros debug_reloc_start and debug_reloc_end were
rendered unused in commit 6d7d0ae51574943bf571d269da3243257a2d15db
"ARM: 6750/1: improvements to compressed/head.S".

Later on a different debug macro named dbgkc was introduced
in commit f3c899927e19d1be39818145efc39ea27b8efc69
"ARM: 8786/1: Debug kernel copy by printing".

Delete the dead debug code.

Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully

EFI on ARM only supports short descriptors, and given that it mandates
that the MMU and caches are on, it is implied tha

ARM: 8985/1: efi/decompressor: deal with HYP mode boot gracefully

EFI on ARM only supports short descriptors, and given that it mandates
that the MMU and caches are on, it is implied that booting in HYP mode
is not supported.

However, implementations of EFI exist (i.e., U-Boot) that ignore this
requirement, which is not entirely unreasonable, given that it makes
HYP mode inaccessible to the operating system.

So let's make sure that we can deal with this condition gracefully.
We already tolerate booting the EFI stub with the caches off (even
though this violates the EFI spec as well), and so we should deal
with HYP mode boot with MMU and caches either on or off.

- When the MMU and caches are on, we can ignore the HYP stub altogether,
since we can carry on executing at HYP. We do need to ensure that we
disable the MMU at HYP before entering the kernel proper.

- When the MMU and caches are off, we have to drop to SVC mode so that
we can set up the page tables using short descriptors. In this case,
we need to install the HYP stub as usual, so that we can return to HYP
mode before handing over to the kernel proper.

Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: decompressor: run decompressor in place if loaded via UEFI

The decompressor can load from anywhere in memory, and the only reason
the EFI stub code relocates it is to ensure it appe

ARM: decompressor: run decompressor in place if loaded via UEFI

The decompressor can load from anywhere in memory, and the only reason
the EFI stub code relocates it is to ensure it appears within the first
128 MiB of memory, so that the uncompressed kernel ends up at the right
offset in memory.

We can short circuit this, and simply jump into the decompressor startup
code at the point where it knows where the base of memory lives. This
also means there is no need to disable the MMU and caches, create new
page tables and re-enable them.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>

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ARM: decompressor: defer loading of the contents of the LC0 structure

The remaining contents of LC0 are only used after the point in the
decompressor startup code where we enter via 'won

ARM: decompressor: defer loading of the contents of the LC0 structure

The remaining contents of LC0 are only used after the point in the
decompressor startup code where we enter via 'wont_overwrite'. So
move the loading of the LC0 structure after it. This will allow us
to jump to wont_overwrite directly from the EFI stub, and execute
the decompressor in place at the offset it was loaded by the UEFI
firmware.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>

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ARM: decompressor: split off _edata and stack base into separate object

In preparation of moving the handling of the LC0 object to a later stage
in the decompressor startup code, move ou

ARM: decompressor: split off _edata and stack base into separate object

In preparation of moving the handling of the LC0 object to a later stage
in the decompressor startup code, move out _edata and the initial value
of the stack pointer, which are needed earlier than the remaining
contents of LC0.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>

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ARM: decompressor: move headroom variable out of LC0

Before breaking up LC0 into different pieces, move out the variable
that is already place-relative (given that it subtracts 'restart'

ARM: decompressor: move headroom variable out of LC0

Before breaking up LC0 into different pieces, move out the variable
that is already place-relative (given that it subtracts 'restart' in
the expression) and so its value does not need to be added to the
runtime address of the LC0 symbol itself.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Nicolas Pitre <nico@fluxnic.net>

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Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:

- replace setup_irq() with request_irq() for ebsa110, footbridge, rpc

Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:

- replace setup_irq() with request_irq() for ebsa110, footbridge, rpc

- fix clang assembly error in kexec code

- remove .fixup section in boot stub

- decompressor / EFI cache flushing updates

* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: 8966/1: rpc: replace setup_irq() by request_irq()
ARM: 8965/2: footbridge: replace setup_irq() by request_irq()
ARM: 8964/1: ebsa110: replace setup_irq() by request_irq()
ARM: 8962/1: kexec: drop invalid assembly argument
ARM: decompressor: switch to by-VA cache maintenance for v7 cores
ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance
ARM: decompressor: factor out routine to obtain the inflated image size
ARM: 8959/1: Remove unused .fixup section in boot stub
ARM: allow unwinder to unwind recursive functions

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efi/arm: Clean EFI stub exit code from cache instead of avoiding it

The following commit:

c7225494b ("efi/arm: Work around missing cache maintenance in decompressor handover")

efi/arm: Clean EFI stub exit code from cache instead of avoiding it

The following commit:

c7225494b ("efi/arm: Work around missing cache maintenance in decompressor handover")

modified the EFI handover code written in assembler to work around the
missing cache maintenance of the piece of code that is executed after the
MMU and caches are turned off.

Due to the fact that this sequence incorporates a subroutine call, cleaning
that code from the cache is not a matter of simply passing the start and end of
the currently running subroutine into cache_clean_flush(), which is why
instead, the code jumps across into the cleaned copy of the image.

However, this assumes that this copy is executable, and this means we
expect EFI_LOADER_DATA regions to be executable as well, which is not
a reasonable assumption to make, even if this is true for most UEFI
implementations today.

So change this back, and add a cache_clean_flush() call to cover the
remaining code in the subroutine, and any code it may execute in the
context of cache_off().

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: linux-efi@vger.kernel.org
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: David Hildenbrand <david@redhat.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Link: https://lore.kernel.org/r/20200228121408.9075-5-ardb@kernel.org

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ARM: decompressor: switch to by-VA cache maintenance for v7 cores

Update the v7 cache_clean_flush routine to take into account the
memory range passed in r0/r1, and perform cache mainten

ARM: decompressor: switch to by-VA cache maintenance for v7 cores

Update the v7 cache_clean_flush routine to take into account the
memory range passed in r0/r1, and perform cache maintenance by
virtual address on this range instead of set/way maintenance, which
is inappropriate for the purpose of maintaining the cached state of
memory contents.

Since this removes any use of the stack in the implementation of
cache_clean_flush(), we can also drop some code that manages the
value of the stack pointer before calling it.

Tested-by: Tony Lindgren <tony@atomide.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

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ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance

In preparation for turning the decompressor's cache clean/flush
operations into proper by-VA maintenance for v7 c

ARM: decompressor: prepare cache_clean_flush for doing by-VA maintenance

In preparation for turning the decompressor's cache clean/flush
operations into proper by-VA maintenance for v7 cores, pass the
start and end addresses of the regions that need cache maintenance
into cache_clean_flush in registers r0 and r1.

Currently, all implementations of cache_clean_flush ignore these
values, so no functional change is expected as a result of this
patch.

Tested-by: Tony Lindgren <tony@atomide.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

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ARM: decompressor: factor out routine to obtain the inflated image size

Before adding another reference to the inflated image size, factor
out the slightly complicated way of loading the

ARM: decompressor: factor out routine to obtain the inflated image size

Before adding another reference to the inflated image size, factor
out the slightly complicated way of loading the unaligned little-endian
constant from the end of the compressed data.

Tested-by: Tony Lindgren <tony@atomide.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

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efi/libstub/arm: Make efi_entry() an ordinary PE/COFF entrypoint

Expose efi_entry() as the PE/COFF entrypoint directly, instead of
jumping into a wrapper that fiddles with stack buffers

efi/libstub/arm: Make efi_entry() an ordinary PE/COFF entrypoint

Expose efi_entry() as the PE/COFF entrypoint directly, instead of
jumping into a wrapper that fiddles with stack buffers and other
stuff that the compiler is much better at. The only reason this
code exists is to obtain a pointer to the base of the image, but
we can get the same value from the loaded_image protocol, which
we already need for other reasons anyway.

Update the return type as well, to make it consistent with what
is required for a PE/COFF executable entrypoint.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

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efi/arm: Pass start and end addresses to cache_clean_flush()

In preparation for turning the decompressor's cache clean/flush
operations into proper by-VA maintenance for v7 cores, pass t

efi/arm: Pass start and end addresses to cache_clean_flush()

In preparation for turning the decompressor's cache clean/flush
operations into proper by-VA maintenance for v7 cores, pass the
start and end addresses of the regions that need cache maintenance
into cache_clean_flush in registers r0 and r1.

Currently, all implementations of cache_clean_flush ignore these
values, so no functional change is expected as a result of this
patch.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

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efi/arm: Work around missing cache maintenance in decompressor handover

The EFI stub executes within the context of the zImage as it was
loaded by the firmware, which means it is treated

efi/arm: Work around missing cache maintenance in decompressor handover

The EFI stub executes within the context of the zImage as it was
loaded by the firmware, which means it is treated as an ordinary
PE/COFF executable, which is loaded into memory, and cleaned to
the PoU to ensure that it can be executed safely while the MMU
and caches are on.

When the EFI stub hands over to the decompressor, we clean the caches
by set/way and disable the MMU and D-cache, to comply with the Linux
boot protocol for ARM. However, cache maintenance by set/way is not
sufficient to ensure that subsequent instruction fetches and data
accesses done with the MMU off see the correct data. This means that
proceeding as we do currently is not safe, especially since we also
perform data accesses with the MMU off, from a literal pool as well as
the stack.

So let's kick this can down the road a bit, and jump into the relocated
zImage before disabling the caches. This removes the requirement to
perform any by-VA cache maintenance on the original PE/COFF executable,
but it does require that the relocated zImage is cleaned to the PoC,
which is currently not the case. This will be addressed in a subsequent
patch.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

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ARM: 8942/1: Revert "8857/1: efi: enable CP15 DMB instructions before cleaning the cache"

This reverts commit e17b1af96b2afc38e684aa2f1033387e2ed10029, which is
no longer necessary now t

ARM: 8942/1: Revert "8857/1: efi: enable CP15 DMB instructions before cleaning the cache"

This reverts commit e17b1af96b2afc38e684aa2f1033387e2ed10029, which is
no longer necessary now that the v7 specific routines take care not to
issue CP15 barrier instructions before they are enabled in SCTLR.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: 8941/1: decompressor: enable CP15 barrier instructions in v7 cache setup code

Commit e17b1af96b2afc38e684aa2f1033387e2ed10029

"ARM: 8857/1: efi: enable CP15 DMB instructions

ARM: 8941/1: decompressor: enable CP15 barrier instructions in v7 cache setup code

Commit e17b1af96b2afc38e684aa2f1033387e2ed10029

"ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache"

added some explicit handling of the CP15BEN bit in the SCTLR system
register, to ensure that CP15 barrier instructions are enabled, even
if we enter the decompressor via the EFI stub.

However, as it turns out, there are other ways in which we may end up
using CP15 barrier instructions without them being enabled. I.e., when
the decompressor startup code skips the cache_on() initially, we end
up calling cache_clean_flush() with the caches and MMU off, in which
case the CP15BEN bit in SCTLR may not be programmed either. And in
fact, cache_on() itself issues CP15 barrier instructions before actually
enabling them by programming the new SCTLR value (and issuing an ISB)

Since these routines are shared between v7 CPUs and older ones that
implement the CPUID extension as well, using the ordinary v7 barrier
instructions in this code is not possible, and so we should enable the
CP15 ones explicitly before issuing them. Note that a v7 ISB is still
required between programming the SCTLR register and using the CP15 barrier
instructions, and we should take care to branch over it if the CP15BEN
bit is already set, given that in that case, the CPU may not support it.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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ARM: 8933/1: replace Sun/Solaris style flag on section directive

It looks like a section directive was using "Solaris style" to declare
the section flags. Replace this with the GNU style

ARM: 8933/1: replace Sun/Solaris style flag on section directive

It looks like a section directive was using "Solaris style" to declare
the section flags. Replace this with the GNU style so that Clang's
integrated assembler can assemble this directive.

The modified instances were identified via:
$ ag \.section | grep #

Link: https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC119
Link: https://github.com/ClangBuiltLinux/linux/issues/744
Link: https://bugs.llvm.org/show_bug.cgi?id=43759
Link: https://reviews.llvm.org/D69296

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Suggested-by: Fangrui Song <maskray@google.com>
Suggested-by: Jian Cai <jiancai@google.com>
Suggested-by: Peter Smith <peter.smith@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

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