# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
# Copyright (C) 2019 Texas Instruments Incorporated
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter

maintainers:
  - Dan Murphy <dmurphy@ti.com>

description: |
  The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
  PDM microphones recording), high-performance audio, analog-to-digital
  converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
  family supports line and  microphone Inputs, and offers a programmable
  microphone bias or supply voltage generation.

  Specifications can be found at:
    http://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
    http://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
    http://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf

properties:
  compatible:
    oneOf:
      - const: ti,tlv320adc3140
      - const: ti,tlv320adc5140
      - const: ti,tlv320adc6140

  reg:
    maxItems: 1
    description: |
       I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f

  reset-gpios:
    description: |
       GPIO used for hardware reset.

  areg-supply:
      description: |
       Regulator with AVDD at 3.3V.  If not defined then the internal regulator
       is enabled.

  ti,mic-bias-source:
    description: |
       Indicates the source for MIC Bias.
       0 - Mic bias is set to VREF
       1 - Mic bias is set to VREF × 1.096
       6 - Mic bias is set to AVDD
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 6]

  ti,vref-source:
    description: |
       Indicates the source for MIC Bias.
       0 - Set VREF to 2.75V
       1 - Set VREF to 2.5V
       2 - Set VREF to 1.375V
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]

  ti,pdm-edge-select:
    description: |
       Defines the PDMCLK sampling edge configuration for the PDM inputs.  This
       array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.

       0 - (default) Odd channel is latched on the negative edge and even
       channel is latched on the the positive edge.
       1 - Odd channel is latched on the positive edge and even channel is
       latched on the the negative edge.

       PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
       PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
       PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
       PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data

    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 4
    items:
      maximum: 1
    default: [0, 0, 0, 0]

  ti,gpi-config:
    description: |
       Defines the configuration for the general purpose input pins (GPI).
       The array is defined as <GPI1 GPI2 GPI3 GPI4>.

       0 - (default) disabled
       1 - GPIX is configured as a general-purpose input (GPI)
       2 - GPIX is configured as a master clock input (MCLK)
       3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
       4 - GPIX is configured as a PDM data input for channel 1 and channel
            (PDMDIN1)
       5 - GPIX is configured as a PDM data input for channel 3 and channel
            (PDMDIN2)
       6 - GPIX is configured as a PDM data input for channel 5 and channel
            (PDMDIN3)
       7 - GPIX is configured as a PDM data input for channel 7 and channel
            (PDMDIN4)

    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 1
    maxItems: 4
    items:
      maximum: 7
    default: [0, 0, 0, 0]

required:
  - compatible
  - reg

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>
    i2c0 {
      #address-cells = <1>;
      #size-cells = <0>;
      codec: codec@4c {
        compatible = "ti,tlv320adc5140";
        reg = <0x4c>;
        ti,mic-bias-source = <6>;
        ti,pdm-edge-select = <0 1 0 1>;
        ti,gpi-config = <4 5 6 7>;
        reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
      };
    };
