# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Global Clock & Reset Controller Binding

maintainers:
  - Stephen Boyd <sboyd@kernel.org>
  - Taniya Das <tdas@codeaurora.org>

description: |
  Qualcomm global clock control module which supports the clocks, resets and
  power domains on SDM845

  See also:
  - dt-bindings/clock/qcom,gcc-sdm845.h

properties:
  compatible:
    const: qcom,gcc-sdm845

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source
      - description: PCIE 0 Pipe clock source
      - description: PCIE 1 Pipe clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk
      - const: pcie_0_pipe_clk
      - const: pcie_1_pipe_clk

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  power-domains:
    maxItems: 1

  '#power-domain-cells':
    const: 1

  reg:
    maxItems: 1

  protected-clocks:
    description:
      Protected clock specifier list as per common clock binding.

required:
  - compatible
  - reg
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  # Example for GCC for SDM845:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,gcc-sdm845";
      reg = <0x100000 0x1f0000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&sleep_clk>,
               <&pcie0_lane>,
               <&pcie1_lane>;
      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...
